This paper presents a multi-objective mixed-integer nonlinear programming model to design a group layout of a cellular manufacturing system in a dynamic environment, in which the number of cells to be formed is variable. Cell formation (CF) and group layout (GL) are concurrently made in a dynamic environment by the integrated model, which incorporates with an extensive coverage of important man...

BACKGROUND Optune™, previously known as the NovoTTF-100A System™, generates Tumor Treating Fields (TTFields), an effective anti-mitotic therapy for glioblastoma. The system delivers intermediate frequency, alternating electric fields to the supratentorial brain. Patient therapy is personalized by configuring transducer array layout placement on the scalp to the tumor site using MRI measurements...

Enhanced Inter Cell Interference Coordination (eICIC) for co-channel deployments of pico cells throughout a macro cell layout is studied. In particular, we analyze a scenario where only some macro cells have picos deployed, while other macro cells have no small cells. The challenge for such highly irregular scenarios is how to operate eICIC, and especially how to coordinate macro-cell muting. O...

We propose an integrated algorithm that will solve the part-family and machinecell formation problem by simultaneously considering the within-cell layout problem. To the best of our knowledge, this is the ® rst study that considers the e ciency of both individual cells and the overall system in monetary terms. Each cell should make at least a certain amount of pro® t to attain self-su ciency,...

The proposed multiplexer-based novel 1-bit full adder cell is schematized by using DSCH2 and its layout is generated by using microwind VLSI CAD tool. The adder cell layout interconnect analysis is performed by using BSIM4 layout analyzer. The adder circuit is compared with other six existing adder circuits for parametric analysis. The proposed adder cell gives better performance than the other...

The in-memory graph layout or organization has a considerable impact on the time and energy efficiency of distributed memory graph computations. It affects memory locality, inter-task load balance, communication time, and overall memory utilization. Graph layout could refer to partitioning or replication of vertex and edge arrays, selective replication of data structures that hold meta-data, an...

Dynamic application layout is the capability to move the components of a distributed program among different hosts during the execution of the application. This capability is essential for large-scale applications since it allows to adapt them to changes in resource availability, which are common in wide-area environments. The FarGo system introduces a model for programming the layout of distri...

To save layout area for electrostatic discharge (ESD) protection design in the SOC era, test chip with large size NMOS devices placed under bond pads has been fabricated in 0.35-μm one-poly-four-metal (1P4M) 3.3V CMOS process for verification. The bond pads had been drawn with different layout patterns on the inter-layer metals to investigate the effect of bonding stress on the active devices u...

High performance embedded architectures will in some cases combine simple caches and multithreading, two techniques that increase energy efficiency and performance at the same time. However, that combination can produce high and unpredictable cache miss rates, even when the compiler optimizes the data layout of each program for the cache. This paper examines data-cache aware compilation for mul...

For text, audio, video, and still images, a number of projects have addressed the problem of estimating inter-object similarity and the related problem of finding transition, or ‘segmentation’ points in a stream of objects of the same media type. There has been relatively little work in this area for document images, which are typically text-intensive and contain a mixture of layout, text-based...