Minimizing program code size reduces power consumption and space, which is especially important in embedded systems. Existing variable-length instruction formats provide higher code densities than fixed-length formats, but are ill-suited to pipelined or parallel instruction fetch and decode. This thesis presents a new variable-length instruction format that supports parallel fetch and decode of...

Compiler-controlled speculation has been shown to be effective in increasing instruction level parullelism (ILP) found in non-numeric programs. However, it is not clear the extent to which speculatively scheduled code may affect the instruction and data caches. In particular, the amount of time spent resolving cache mis.qes may be significant enough to prevent the more aggressitle speculation m...

show frequently 20% to 50% reduction in instruction cache misses. By better utilizing window statistical metrics to study memory behaviors (15). (18), (6), (16). 153, Cache miss equations: a compiler framework for analyzing and tuning memory 40, Predicting instruction cache behavior Mueller, Whalley, et al. Stephan Müller [email protected]_ and the maintenance and behavior of entropy is disc...

Compiler-controlled speculation has been shown to be e ective in increasing instruction level parallelism (ILP) found in non-numeric programs. However, it is not clear the extent to which speculatively scheduled code may a ect the instruction and data caches. In particular, the amount of time spent resolving cache misses may be signi cant enough to prevent the more aggressive speculation models...

This paper introduces a new method for instruction cache analysis that outperforms conventional tracedriven methods. The new method, static cache simulation, analyzes a program for a given cache configuration and determines prior t o execution time if an instruction reference will always result in a cache hit or miss. At run time, counters are incremented to provide the execution frequency of p...

In multitasking real-time systems it is required to compute the WCET of each task and also the effects of interferences between tasks in the worst case. This is very complex with variable latency hardware, such as instruction cache memories, or, to a lesser extent, the line buffers usually found in the fetch path of commercial processors. Some methods disable cache replacement so that it is eas...

This paper describes a new hardware approach to data and instruction prefetching for superscalar processors. The key innovation is instruction prefetching by predicting procedural control ow, and decoupling data and instruction prefetching. Simulation results show this method to recover 72% of unnecessarily lost cache cycles and to yield a great improvement (20-27%) over previous hardware prefe...

Poor instruction cache locality can degrade performance on modern architectures. For example, our simulation results show that eliminating all instruction cache misses improves performance by as much as 16% for a modestly sized instruction cache. In this paper, we show how to take advantage of dynamic code generation in a Java Virtual Machine (VM) to improve instruction locality at run-time. We...