This paper presents a method to estimate the delay of interconnections. It uses a simple model based exclusively on point to point interconnections, The method has a very low complexity so it can be used during the clock cycle selection in a High Level Synthesis process. In this way it is possible to settle securely the right electrical behavior of the final circuit

Gold–style language learning is a formal theory of learning from examples by algorithmic devices called learning machines. Originally motivated by child language learning, it features the algorithmic synthesis (in the limit) of grammars for formal languages from information about those languages. In traditional Gold–style language learning, learning machines are not provided with negative infor...

Vector field visualization techniques are subdivided into three categories: global, geometric, and feature-based techniques. We describe each category, and we present some related work and an example in each category from our own recent research. Spot Noise is a texture synthesis technique for global visualization of vector fields on 2D surfaces. Deformable surfaces is a generic technique for e...

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We examine the application of High Level Synthesis to FPGA based computing systems. Our experience shows that high level synthesis allows for a level of design space exploration unrealizeable with register transfer level techniques. In addition, the use of high level tools allow designers to prototype their designs with high quality results and fast design turn around times. Our design ow makes...

We present an improved method for scheduling speculative data paths which relies on cancel tokens to undo computations in misspeculated paths. Performancewise, this method is considerably faster than lenient execution, and faster than any other known approach applicable for general (including non-pipelined) computation structures. We present experimental evidence obtained by implementing our me...

This paper introduces a general scheme for formally embedding high level synthesis by formulating its basic steps as transformations within higher order logic. A functional representation of a data ow graph is successively reened by means of generic logical transformations. Algorithms that are based on logical transformations guarantee \correctness by design". They not only construct an impleme...

The growing design-productivity gap has made designers shift toward using high-level languages like C, C++ and Java to do system-level design. High-Level Synthesis (HLS) is the process of generating Register Transfer Level (RTL) design from these initial high-level programs. Unfortunately, this translation process itself can be buggy, which can create a mismatch between what a designer intends ...

This paper presents the detailed survey of scheduling and allocation techniques in the High Level Synthesis (HLS) presented in the research literature. It also presents the methodologies and techniques to improve the Speed, (silicon) Area and Power in High Level Synthesis, which are presented in the research literature.

This paper presents an integer linear programming (ILP) model for the scheduling problem in high level synthesis. In addition to time-constrained scheduling and resource-constrained scheduling, a new scheduling problem called feasible scheduling is constructed, which provides a paradigm for exploring the solution space. Extensive consideration is given to the following applications: scheduling ...