KCNE β-subunits assemble with and modulate the properties of voltage-gated K(+) channels. In the colon, stomach, and kidney, KCNE3 coassembles with the α-subunit KCNQ1 to form K(+) channels important for K(+) and Cl(-) secretion that appear to be voltage-independent. How KCNE3 subunits turn voltage-gated KCNQ1 channels into apparent voltage-independent KCNQ1/KCNE3 channels is not completely und...

Based on fluoride-based plasma treatment of the gate region in AlGaN/GaN HEMTs and post-gate rapid thermal annealing (RTA), enhancement mode (E-mode) AlGaN/GaN HEMTs with low on-resistance and low knee-voltage were fabricated. The fabricated E-mode AlGaN/GaN HEMT with 1 μm-long gate exhibits a threshold voltage of 0.9 V, a kneevoltage of 2.2 V, a maximum drain current density of 310 mA/mm, a pe...

We have investigated the surface morphology of electrically stressed AlGaN/GaN high electron mobility transistors using atomic force microscopy and scanning electron microscopy after removing the gate metallization by chemical etching. Changes in surface morphology were correlated with degradation in electrical characteristics. Linear grooves formed along the gate edges in the GaN cap layer for...

An analytical model of the threshold voltage variance induced by random dopant fluctuations (RDF) in junctionless (JL) FETs is derived for both cylindrical nanowire (NW) and planar double-gate (DG) structures considering only the device electrostatics in subthreshold. The model results are shown to be in reasonable agreement with TCAD simulations for different gate lengths and device parameters...

In this paper we present novel ultra-low-voltage and high-speed CMOS NAND and NOR gates. For supply voltages below 500mV the delay for an ultra-low-voltage NAND2 gate is approximately 10% of a complementary CMOS inverter. Furthermore, the delay variations due to mismatch are much lesser than for conventional CMOS. Differential domino gates for AND2/NAND2 and OR2/NOR2 operation are presented. Ul...

As technology feature size is reduced, ESD becomes the dominant failure mode due to lower gate oxide breakdown voltage. In this paper, the effectiveness of new gate and substrate triggering techniques has been investigated to lower the trigger voltage of the LVTSCR and MOSFET based ESD protection circuits using 2D simulations and HBM/TLP measurements. The simulation results show that the using ...

In this study, a laterally coupled device composed of a photodiode and a Si nanowires-field-effect transistor (NWs-FET) is constructed on a plastic substrate and the coupled device is characterized. The photodiode is made of p-type Si NWs and an n-type ZnO film. The Si NWs-FET is connected electrically to the photodiode in order to enhance the latter's photocurrent efficiency by adjusting the g...

This paper explores the advantages and implementation of Digital Signal Processing (DSP) TMS 320F2812 to generate gate pulses. The main features of this DSP are elaborated. The technique to obtain gate pulses in different pulse width modulation methods in order to control three-phase voltage source inverter is explained systematically. The steps needed to develop the program are highlighted in ...

The influence of a gate voltage on domain wall (DW) propagation is investigated in ultrathin Pt/Co/gadolinium oxide (GdOx) films with perpendicular magnetic anisotropy. The DW propagation field can be enhanced or retarded by an electric field at the Co/GdOx interface and scales linearly with gate voltage up to moderate bias levels. Higher gate voltage levels, corresponding to electric fields >0...