Fractional-N PLL is an essential part of modern wireless communication systems. The ever-increasing demand for higher data transfer rates while operating in heavily crowded frequency bands demands top-notch performance from the frequency synthesizers. In order to satisfy the tough requirements put forth by modern communication standards, researchers around the world have examined many innovativ...

In this paper, we propose a speedup method of frequency switching time in the phase locked loop (PLL) frequency synthesizer using the target frequency detector (TFD). The TFD detects the time Ta for any channels where the output of the PLL frequency synthesizer reaches the target frequency for the first time. At Ta, the programmable divider, the reference divider and the phase comparator are re...

GSM & EDGE base-stations require synthesizers that can frequency hop over the full 75MHz TX or RX band in < 10us and also have very low phase noise and spurious. To date, these conflicting requirements can only be accomplished using a costly "ping-pong" architecture where one synthesizer is locking to the next desired frequency while the other is active as the LO. The proposed fast switching sy...

There are several compression methods for phase to amplitude converter for sine function. In this paper, the linear and parabolic approximation of equi-section division utilizing the symmetry property and amplitude approximation of a sinusoidal waveform for direct digital frequency synthesizer (DDS) and also for other waveform applications, e.g. function generators and telecommunication devices...

This paper presents a frequency synthesizer architecture based on the time delay digital tanlock loop (TDTL). The loop is of the first order type. The synthesizer architecture includes an adaptation mechanism to keep the complete system in lock. The mechanism uses a frequency sensing structure to control critical TDTL parameters responsible for locking. Both integer and fractional multiples of ...

The demand for lower cost, lower power, and multiband RF circuits increased in conjunction with need of higher level of integration. In this project a low-power singlephase clock multiband flexible divider for Bluetooth, Zigbee, and Network standard’s 802.15.4 and 802.11 a/b/g Wireless LAN frequency synthesizers is proposed based on pulse-swallow topology and is implemented. The frequency synth...

The phase selection technique is a good solution to design programable dividers widely used in fractional synthesizers. However, as the process parameters vary, the delays in the phase selection logic change, and they erroneously trigger the phase selection. This paper presents an improvement that consists on making the phase selection logic in a semi sequential fashion. In this way if there is...

Thanks to its ability to generate a stable yet programmable output frequency, Phase Locked Loop (PLL) frequency synthesizers are found in most modern radio transceivers. All practical PLL implementations suffer from unwanted frequency components such as phasenoise and spurious tones, and since these components affect system performance they must be predicted and minimized. This thesis discuss t...

By Zhihe Zhou, Ph.D. Washington State University August 2006 Chair: George S. La Rue We investigated the design and implementation of non-linear D/A converters (DAC) for a direct digital frequency synthesizer (DDFS), which consists of a phase accumulator, a phase-to-sine look-up table and a DAC. Using a non-linear DAC can significantly reduce the look-up table size, hence, reducing the power di...