A monolithic 8-bit 250 megasarnple per second analog-todigii at converter (ADC) fabricated in an oxide-isolated bipolar process is deseribed. Using a flash ADC architecture at high speeds without a sample and hold leads to a number of error sources discussed in this paper. The design of the converter is optimized to miuimize the effects of these error sources. Experimental results are presented...

+ Katholieke Universiteit Leuven, Kasteelpark Arenberg 10, B-3001 Heverlee, [email protected] . Abstract The design plan and measurement results of a very high-speed 6 bit CMOS Flash ADC converter are presented. The very high acquisition speed is obtained by improved comparator design. At these high frequencies power-efficient error correction logic is necessary. Measurements show th...

This paper presents a 12-bit 2.32 GS/s time-interleaved pipelined/successive-approximation register (SAR) hybrid analog-to-digital converter (ADC) implemented in 28 nm CMOS. To achieve high-linearity at several GS/s, pseudo-differential push-pull input buffer with floating-body technique is proposed. A pipelined/SAR architecture dual-channel sampling multiplying digital-to-analog (MDAC) and one...

The purpose of this paper is to design a prevented glitch circuit (PGC) to avoid the destroyed that is caused to glitch in the paralleling comparator Flash ADC. The advantages of this prevented glitch circuit are high-speed, lower power consumption, and size effective, furthermore, it also reduce the faults. We used the TSPC’s D flip-flop to achieve this prevented glitch circuit where reduces a...

A 2.5 GS/s flash ADC, fabricated in 90nm CMOS utilizes comparator redundancy to avoid traditional power, speed and accuracy trade-offs. The redundancy removes the need to control comparator offsets, allowing the large process-variation induced mismatch of small devices in nanometer technologies. This enables the use of small-sized, ultra-low-power comparators with clock-gating capabilities in o...

The paper presents a color sensor system that can process light reflected from a surface and produce a digital output representing the color of the surface. The end-user interface circuit requires only a 3-bit pseudo flash analog-to-digital converter (ADC) in place of the conventional/typical design comprising ADC, digital signal processor and memory. For scalability and compactness, the ADC wa...

Flash analog-to-digital converters, also known as parallel ADCs, are the fastest way to convert an analog signal to a digital signal. Flash ADCs are ideal for applications requiring very large bandwidth, but they consume more power than other ADC architectures and are generally limited to 8-bit resolution. This tutorial will discuss flash converters and compare them with other converter types. ...

In this paper, we present a complete design methodology for high-performance low-power Analog-to-Digital Converters in deep submicron CMOS. This methodology is demonstrated on two ADC architectures, Flash and Folding&Interpolating(F&I). The designs were implemented in 0.18μm CMOS technology, achieving a high conversion rate of 2.6 GSamples/s for the Flash converter, and a 1 GSample/s rate for t...

The thermometer code-to-binary code encoder has become the bottleneck of the ultra-high speed flash ADCs. In this paper, the authors presented the fat tree thermometer codeto-binary code encoder that is highly suitable for the ultrahigh speed flash ADCs. The simulation and the implementation results show that the fat tree encoder outperforms the commonly used ROM encoder in terms of speed and p...