Abstract We study two-qubit circuits over the Clifford+CS gate set, which consists of Clifford gates together with controlled-phase CS = diag(1, 1, i ). The set is universal for quantum computation and its elements can be implemented fault-tolerantly in most error-correcting schemes through magic state distillation. Since non-Clifford are typically more expensive to perform a fault-tolerant man...

Quantum-dot cellular automata (QCA) are an emerging technology and a possible alternative for faster speed, smaller size, and low power consumption than semiconductor transistor based technologies. Previously, adder designs based on conventional designs were examined for implementation with QCA technology. This paper utilizes the QCA characteristics to design a fault-tolerant adder that is more...

Quantum-dot cellular automata (QCA) are an emerging technology and a possible alternative for faster speed, smaller size, and low power consumption than semiconductor transistor based technologies. Previously, adder designs based on conventional designs were examined for implementation with QCA technology. This paper utilizes the QCA characteristics to design a fault-tolerant adder that is more...

In parity preserving reversible circuit, the parity of the input vector must match the parity of the output vector. It renders a wide class of circuit faults readily detectable at the circuit’s outputs. Thus reversible logic circuits that are parity preserving will be beneficial to the development of fault tolerant systems in nanotechnology. This paper presents an efficient realization of well ...

The work demonstrates about the reversible logic synthesis for the 2 to 4 decoder, the circuits are designed using reversible fault tolerant toffoli gates. Thus the entire scheme inherently becomes fault tolerant. In addition, several lower bounds on the number of constant inputs, garbage outputs and quantum cost of the reversible fault tolerant decoder have been proposed. Transistor simulation...

This paper presents a five-phase fault-tolerant permanent-magnet synchronous machine (PMSM) used for electric vehicles. In multiphase fault-tolerant PMSMs equipped with fractional-slot concentrated windings, excessive magneto-motive force (MMF) harmonics can lead to thermal demagnetization of the permanent magnets (PMs). In order to reduce the lower-order harmonics, the origins of the 2-pole ha...

An arbitrarily reliable quantum computer can be efficiently constructed from noisy components using a recursive simulation procedure, provided that those components fail with probability less than the fault-tolerance threshold. Recent estimates of the threshold are near some experimentally achieved gate fidelities. However, the landscape of threshold estimates includes pseudothresholds, thresho...

Asynchronous circuit design is a promising technology for large-scale multi-core systems. As a family of asynchronous circuits, Quasi-delay-insensitive (QDI) circuits have been widely used to build chip-level long interconnects due to their tolerance to delay variations. However, QDI interconnects are vulnerable to faults. Traditional fault-tolerant techniques for synchronous circuits cannot be...

We provide a rigorous analysis of fault-tolerant quantum computation in the presence of local leakage faults. We show that one can systematically deal with leakage by using appropriate leakage-reduction units such as quantum teleportation. The leakage noise is described by a Hamiltonian and the noise is treated coherently, similar to general non-Markovian noise analyzed in Refs. [TB05] and [AGP...

In this paper, a cost-efficient fault-tolerant router design, called 20-Path Router (20PR) architecture, is proposed to reduce the impacts of faulty routers for 2D-mesh based chip multiprocessor systems. The 20PR consists of two fault-tolerant circuits: 1) a Builtin Self-Test and Self-Diagnosis (BIST/SD) circuit to detect and locate faulty FIFOs and MUXs, and 2) a Fault-Isolation (FI) circuit t...