RC4 Stream cipher is well known for its simplicity and ease to develop in software. But here, in the proposed design we have heighlighted the modified hardware implémentation of RC4. As RC4 is the most popular stream cipher. The proposed design performs reading and swapping simultaneously in one clock cycle. The proposed design also highlights the adder part which enhances the architecture spee...

The multiplier forms the core of systems such as FIR filters, Digital Signal Processors and Microprocessors etc. This paper presents a model of two different 16X16 bit multipliers. First is Radix-4 Multiplier with SQRT CSLA and Second one is Radix -4 multiplier with Modified SQRT CSLA. Modified Booth Algorithm is used for Partial Products Generation. Wallace Tree Structure is used to accumulate...

In this paper, high speed carry skip adders for two different circuits were proposed. In the conventional structure of CSKA consists of a chain of ripple carry adder (RCA) block and 2:1 multiplexer. In the proposed structure, parallel prefix adder network is used to improve the speed and energy parameters. In addition to this the proposed structure called AND-OR-Invert (AOI) and OR-ANDInvert (O...

Output Prediction Logic (OPL) is a technique that can be applied to conventional CMOS logic families to obtain considerable speedups. When applied to static CMOS, OPL retains the restoring character of the logic family. Speedups of 2x10 3X over (optimized) conventional static CMOS are demonstrated for a variety of circuits, ranging from chains of gates, to datapath circuits, and to random logic...

In this paper VHDL implementation of 8-bit arithmetic logic unit (ALU) is presented. The design was implemented using VHDL Xilinx Synthesis tool ISE 13.1 and targeted for Spartan device. ALU was designed to perform arithmetic operations such as addition and subtraction using 8-bit fast adder, logical operations such as AND, OR, XOR and NOT operations, 1’s and 2’s complement operations and compa...

This paper proposes a methodology for the development of simple arithmetic self­ checking circuits using Signed Digit representation. In particular, the architecture of an adder is reported and its selfchecking capability with respect to the stuck-at fault set is shown. The main idea underlying the paper is to exploit the properties of Signed Digit representation allowing carry-free operations....

Based on an algorithm derived from the New Chinese Remainder Theorem I, we present three new residue-to-binary converters for the residue number system (2 1 2 2 + 1) designed using 2 -bit or -bit adders with improvements on speed, area, or dynamic range compared with various previous converters. The 2 -bit adder based converter is faster and requires about half the hardware required by previous...

This paper presents a novel method of hardware reduced fast FIR filter structure for parallel data processing.In general, arithmetic operation modules such as adder and multiplier modules, consume much power, energy, and circuit area. The power consumed by the adder structure is also very significant while designing a low power filter. The proposed low power multipliers and low power adders are...

This study presents efficient algorithms for performing multiply-by-3 (3N) and divide-by-3 (N/3) operations with the additions and subtractions, respectively. No multiplications and divisions are needed. Full adder (FA) and full subtractor (FS) can be implemented to realize the N3 and N/3 operations, respectively. For fast hardware implementation, this paper introduces two basic cells UCA and U...

In this paper, the implementation of residue number system reverse converters based on hybrid parallel prefix adders is analyzed. The parallel prefix adder provides high speed and reduced delay arithmetic operations but it is not widely used since it suffers from high power consumption. Hence, a hybrid parallel prefix adder component is presented to perform fast modulo addition in Residue Numbe...