Simulation and modeling of gate tunneling current for thin-oxide MOSFETs and Double-Gate SOIs are discussed. Guidelines for design of leaky MOS capacitors are proposed. Resonant gate tunneling current in DG SOI is simulated, based on quantum-mechanical models, and shown to be an issue of growing concern.

Circuit-performance implications for double-gate MOSFET scaling in the sub-25 nm gate length regime are investigated. The optimal gate-to-source/drain overlap needed to maximize drive current is found to be different than that needed to minimize FO-4 inverter delay due to parasitic capacitances. It is concluded that the effective channel length must be slightly larger than the physical gate len...

We have studied electron mobility behavior in asymmetric double-gate silicon on insulator ~DGSOI! inversion layers, and compared it to the mobility in symmetric double-gate silicon on insulator devices, where volume inversion has previously been shown to play a very important role, being responsible for the enhancement of the electron mobility. Poisson’s and Schroedinger’s equations have been s...

Degradation phenomena due to hot carrier stress conditions were investigated in double-gate polysilicon thin film transistors fabricated by sequential lateral solidification (SLS). We varied the hot carrier stress conditions at the front gate channel by applying various voltages at the back-gate. Thus, we investigated the device electrical performance under such stress regimes. As a conclusion,...

Vertically grown carbon nanotubes have the potential for tera-level integration. However, the well-known ambipolar behavior limits the performance of carbon nanotube field effect transistors. In this work we demonstrate that a double gate structure effectively suppresses the ambipolar behavior. Using the double gate design excellent device characteristics along with the potential for high scale...

According to Moore’s law, the number of transistor embedded on integrated circuit (IC) doubles approximately every two years. Thus, the size of Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) has to be scaled down as an increase in packing density. In current technology, the size of a transistor has shrunk below 45nm, and it has already reached its physical limit. Any attempt to shri...