The bone marrow and thymus, although both hemopoietic environments, induce very distinct differentiation outcomes. The former supports hemopoietic stem cell self-renewal and multiple hemopoietic lineages, while the latter supports T lymphopoiesis almost exclusively. This distinction suggests that the thymic environment acts to restrict the hemopoietic fates available to thymic immigrants. In th...

In butterflies there is a class of "intervein" wing patterns that have lines of symmetry halfway between wing veins. These patterns occur in a range of shapes, including eyespots, ellipses, and midlines, and were proposed to have evolved through developmental shifts along a midline-to-eyespot continuum. Here we show that Notch (N) upregulation, followed by activation of the transcription factor...

An 86-year-old female patient from northeast Mexico presented with diffuse lepromatous leprosy (DLL). Sequence analysis of four genes (rrs, rpoB, sigA, and hsp65) from the skin biopsy specimen identified "Mycobacterium lepromatosis." This is the first independent confirmation of a case of DLL due to M. lepromatosis.

In this paper, we present a novel approach to comprehensively verify timing sensitive blocks, specifically Delay Lines and Delay Locked Loops by modelling transient behavior into the RTL. This paper focuses on reduction of simulation time and increase in design turnaround time. Information gathered from a small set of spice simulations is modelled into a Verilog based environment, which gives s...

In this work, we present a 200 MHz to 1.6 GHz digital delay-locked loop (DLL) for per-pin deskew applications. The proposed phase shifters apply linear and scalable circuit architecture for the pin-to-pin delay mismatch of parallel I/O pins. The proposed phase detector with a detection window and the proposed consecutive phase decision method reduce the sensitivity to reference clock jitter. A ...

Received Mar 17, 2017 Revised Sep 8, 2017 Accepted Sep 20, 2017 Delay locked loop is a critical building block of high speed synchronous circuits. An improved architecture of amixed signaldelay locked loop (DLL) is presented here. In this DLL, delay cell based on single ended differential pair configuration is used for voltage controlled delay line (VCDL) implementation. This delay cell provide...

OBJECTIVE To investigate the relationship between Notch-signaling pathway and familial adenomatous polyposis (FAP) through the expressions of Notch-1, DLL-1, and p-mTOR, and to explore its correlation with tumorigenesis. MATERIALS AND METHODS The expressions of Notch1, DLL-1, and p-mTOR were detected in 21 cases of FAP polyps, 20 cases of colorectal inflammatory polyp, and 20 cases of poorly ...

In this paper, we analyze a noise-to-jitter transfer function on DLL (Delay Locked Loop) considering power supply noise effects on PDN (Power Distribution Network). Noise-tojitter transfer function of DLL circuit can be estimated by using single-tone power supply noise analysis. Noise transfer function through the PDN can be obtained from transfer impedance of hierarchical PDN using TLM (Transm...

This paper describes a low-voltage, low-jitter clock synthesizer and a temperaturecompensated tunable oscillator. Both of these circuits employ a self-correcting Delay-Locked Loop (DLL) which solves the problem of false locking associated with conventional DLLs. This DLL does not require the delay control voltage to be set on power-up, it can recover from missing reference clock pulses and beca...

Leading algorithms for Boolean satisfiability (SAT) are based on either a depth-first tree traversal of the search space (the DLL procedure [6]) or resolution (the DP procedure [7]). In this work we introduce a variant of BreadthFirst Search (BFS) based on the ability of Zero-Suppressed Binary Decision Diagrams (ZDDs) to compactly represent sparse or structured collections of subsets. While a B...