In any digital circuit surface area and power both are very important parameters. In this paper 4bit full adder using transmission gate is designed. To design 4bit full adder two methods are used. First is semi custom design method and second is full custom design method. In first semi custom design method a layout of 4-bit full adder is designed with available width and length of the transisto...

The power-delay product is a direct measurement of the energy expanded per operational cycle of an arithmetic circuit. Lowering the supply voltage of the full adder cell to achieve low power-delay product is a sensible approach to improve the power efficiency at sustainable speed of arithmetic circuits composed of such instances at high level design. In this paper, a novel design of a low power...

Addition is one of the vital parts of any electronic system design because every electronic system needs this basic operation. Researchers have done a lot of work on various adders to optimise their performance. So, they found that Carry Save adder is best in terms of delay calculation and power consumption. That is why this proposed work use this adder. This paper is primarily focus on design ...

Integrated Circuit (IC) Technology is growing day by day to enhance the circuit performance and to increase the density for compact systems. Conventional CMOS technology is playing a vital role in digital computation for past four decades. But there are certain challenges in scaling the CMOS devices for the last few years. A novel technology “Quantum dot Cellular Automata (QCA)” has been identi...

Recently, the influence of the silicon area on the delay time, power dissipation and the leakage current is a crucial issue when designing a full adder circuit. In this paper, an efficient full adder design referred to as 10-T is proposed. The new design utilized the use of XNOR gates instead of XOR in the full adder implementation and, as a result, the delay time and power dissipation are sign...

This paper presents the design and implementation of a time driven adder generator architecture. There exists a large variety of adders designed to satisfy different computation requirements, in particular we list the Carry Look Ahead (CLA) adder, the skip adder, the ripple adder, the carry select adder (CSA), etc. These different architectures will offer different delays and it is up to the us...

Continuous scaling of the transistor size and reduction of the operating voltage has led to a significant performance improvement of integrated circuits. Low power consumption and smaller area are some of the most important criteria for the fabrication of DSP systems and high performance systems. In this paper there is try to determine the best solution to this problem by comparing a few adders...

We present eight new designs for 1-bit full adder cell featuring hybrid CMOS logic style. These designs are based on a novel XOR-XNOR circuit that simultaneously produces XOR and XNOR full-swing outputs and outperforms its best counterpart showing 39% improvement in PDP. The new full-adder designs are also categorized in three main categories depending upon the implementation of the logic expre...