A modified static CMOS inverter with two inputs and two outputs is proposed to reduce short-circuit current in order to increment delay and reduce power overhead where slow operation is required. The circuit is based on bidirectional delay element connected in series with the PMOS and NMOS switching transistors. It provides differences in the dynamic response so that the direct-path current in ...

Various measurement and control systems use magnetic or optical encoders that transform linear displacement and other physical quantities to an analogue quadrature signal. In this paper, we study the problem of, how to accurately delay the analogue quadrature signals in the Sin/Cos encoders within the range of ±10° with the circuit that is potentially integrable on a single chip. Such precision...

Noise eeects such as power supply and crosstalk noise can signiicantly impact the performance of deep submicron designs. Existing timing analysis tecniques cannot capture the eeects of noise on the signal/cell delays. This is because these delay eeects are highly input pattern dependent. Therefore, the predicted circuit performance might not reeect the worst-case circuit delay. In this paper, w...

This paper describes the design and development of a pulse selector circuit, two different low cost techniques for generation of low jitter variable delays and a high band width line driver for use in the regenerative amplifier stage of a table top Terawatt femto second laser chain. The pulse selector stage selects one pulse from a high frequency laser oscillator, injects it into the regenerati...

This paper describes the design of a delay-insensitive (DI) Cell Matrix. This architecture allows for massively parallel, self-determined operation and can be used to implement regular digital circuits or new types of circuits for nanocomputing systems. One advantage of this cell matrix compared to its synchronous counterpart is the delay-insensitive asynchronous nature. This architecture does ...

3-D technology promises higher integration density and lower interconnection complexity and delay. At present, however, not much work on circuit applications has been done due to lack of insight into 3-D circuit architecture and performance. In this paper, we investigate the interconnect distributions of 3-D circuits. We divide the 3-D interconnects into horizontal wires and vertical wires and ...

The Vector Integration to Endpoint (VITE) circuit describes a real-time neural network model simulating behavioral and neurobiological properties of planned arm and hand movements by the interaction of two populations of neurons. We analyze the speed-accuracy trade-off generated by this circuit, generalized to include delayed feedback. With delay, two important new properties of the circuit eme...

This paper provides a theoretical basis for eliminating or reducing the energy consumption due to transients in a synchronous digital circuit The transient energy is minimized when every gate has no more than one output transition per clock cycle This condition is achieved for a gate when the gate delay equals or exceeds the maxi mum di erence between path delays at gate inputs In practice path...

We present a timed automaton-based method for accurate computation of the delays of combinational circuits. In our method, circuits are represented as networks of timed automata, one per circuit element. The state space of the network represents the evolution of the circuit over time and delay is computed by performing a symbolic traver-sal of this state space. Based on the topological structur...

| With the growing scale of integration and the increased use of battery operated devices the power dissipation of CMOS circuits becomes an important factor in the design process. Power dissipation in CMOS-gates depends on the capacity switched and the transition density. Gate sizing is used to scale gates and their internal capacities. Smaller gates mean smaller capacities and therefore less p...