In this paper we propose a practical approach for on-chip inductance extraction. This approach differs from previous methods in that it uses circuit characteristics to obtain a sparse, stable and symmetric inductance matrix, using the concept of resistance dominant and inductance dominant lines. Experimental results show that only the important inductance terms related to strong inductance coup...

We propose two practical approaches for on-chip inductance extraction to obtain a highly sparsified and accurate inverse inductance matrix K. Both approaches differ from previous methods in that they use circuit characteristics to obtain a sparse, stable and symmetric K, using the concept of resistance-dominant and inductance-dominant lines. Specifically, they begin by finding inductance-domina...

Model reduction is a popular approach for incorporating detailed physical effects into high level simulations. In this paper we present a simple method for automatically extracting macromodels of nonlinear circuit with time-varying operating points. The models we generate are truly "reduced", meaning that the complexity of macromodel evaluation is not strongly dependent on the size or complexit...

A characterization methodology to model interconnect capacitance for accurate circuit simulation is presented. The method utilizes a simple measurement scheme to measure inter-layer capacitances. The measured data is then used to tune a layout tool for accurate interconnect parasitic extraction. Results show good fit between simulated and measured ring oscillator speeds for a production 0.5μm, ...

Direct parameter extraction is believed to be the most accurate method for equivalent-circuits modeling of heterojunction bipolar transistors (HBT’s). Using this method, the parasitic elements, followed by the intrinsic elements, are determined analytically. Therefore, the quality of the extrinsic elements extraction plays an important role in the accuracy and robustness of the entire extractio...

A power VDMOSFET has been simulated using PISCES-II, a 2-D numerical device simulator. The doping densities and device dimensions are chosen so as to simulate a typical device structure with one micron channel length. These simulations are aimed at understanding the device physics through various internal electrical quantities like potential distribution, electric field distribution, and electr...

This paper presents an overview of the noise modeling extraction methods developed at the Microwave Electronics Laboratory at Chalmers University of Technology. The presented methods are suitable for different kinds of noise models, the one and two parameter Pospieszalski model, and the three parameter PRC model. We also present a low power low noise amplifier. Introduction To facilitate the de...

We report an accurate and practical method of estimating interconnect capacitances for a given circuit layout. The method extraction of the complete circuit level capacitances at each node in the circuit. The layout geometry is reduced into base elements that consist of different vertical profiles at each node in the layout. Accurate analytical models are developed for calculating capacitances ...