This paper presents CMOS circuits for integrated analog filters at very high frequencies, based on transconductance-C integrators. First a differential transconductance element based on CMOS inverters is described. With this circuit a linear, tunable integrator for very-high-frequency integrated filters can be made. This integrator has good linearity properties (1% relative gm error for 2-V,, i...

This brief presents the architecture and implementation of an analog processor, which in a way akin to a digital microprocessor, embodies a physical model of the universal Turing machine. The analog microprocessor (A P) executes software programs, while nevertheless operating on analog sampled data values. This enables the design of mixed-mode systems which retain the speed/area/power advantage...

In this paper a new 8-bit 50-Msample/s CMOS digital-to-analog converter (DAC) is presented. The circuit employs 9 operational transconductance amplifiers (OTAs) and CMOS transistors as switching circuit. The proposed DAC is simulated using SPICE simulation program with 3μm CMOS technology. Simulation results shows verify good performance of the circuit.

A Continuous-Time Analog Circuit for Computing Time Delays Between Signals Chiang-Jung Pu and John G. Harris University of Florida EE Dept., 446 CSE Bldg 42 Gainesville, FL 32611 Abstract| We describe an analog VLSI circuit that computes the time delay between an arbitrary input signal and its delayed version. Versions of this circuit will be used as the basic computational elements for human a...

ICID (Integrated Circuit IDentification) is a small mixed-signal cell that can be added to the test logic on a CMOS integrated circuit. It provides a unique 224 bit identification number that can be accessed during die test. This identification can be used to correlate test information for individual die on the wafer, through package test, and into the field and back. The identification bits ar...

A parallel algorithm for finding Ramsey numbers is presented where analog/digital CMOS circuits for the hysteresis McCulloch-Pitts binary neuron are described. The hysteresis McCulloch-Pitts binary neuron model is used in order to suppress the oscillatory behaviors of neural dynamics so that the convergence time is shortened. The proposed algorithm using the hysteresis McCultoch-Pitts binary ne...

A 4 bit very low power and low incoming signal analog to digital converter (ADC) using a double sampling switched capacitor technique, designed for use in CMOS monolithic active pixels sensor readout, has been implemented in 0.35μm CMOS technology. A nonresetting sample and hold stage is integrated to amplify the incoming signal by 4. This first stage compensates both the amplifier offset effec...

As great advancements have been made in CMOS process technology over the past 20 years, RF CMOS circuits operating in the microwave band have rapidly developed from component circuit levels to multiband/multimode transceiver levels. In the next ten years, it is highly likely that the following devices will be realized: (i) versatile transceivers such as those used in software-defined radios (SD...

Optimization of a circuit by transistor sizing is often a slow, tedious and iterative manual process which relies on designer intuition. It is highly desirable to automate the transistor sizing process towards being able to rapidly design high performance integrated circuit. Presented here is a simple but effective algorithm for automatically optimizing the circuit parameters by exploiting the ...

this paper presents a design of an uwb downconversion integrated cmos resistive ring mixer with linear voltage regulator (lvr), to supply required biasing voltages for the mixer section. the designed mixer circuit has been optimized for using in heart rate extraction system with microwave doppler radar at 2.4ghz frequency. this mixer needs 2 dc bias voltages equal to 0.5 and 1 volts for its bes...