Block layout dimension prediction is an important activity in many VLSI design tasks (structural synthesis, oorplanning and physical synthesis). Block layout dimension prediction is harder than block area prediction and has been previously considered to be intractable [6]. In this paper we present a solution to this problem using a neural network machine learning paradigm. Our method uses a neu...

In this paper, we describe the latest version of the layout-to-circuit extractor Space. Space can be used to accurately extract circuits, which is increasingly important for high-speed circuits. The program recognizes MOS devices as well as bipolar devices. It computes (Spice) simulation models for bipolar devices based on layout parameters like emitter area, emitter perimeter and base width. F...

This paper describes verification techniques that have been implemented as part of an interactive symbolic IC des ign system. Circuit analysis programs perform node extraction and gate decomposition. They generate both transistor and gate level circuit desriptions which are used as input to a transistor level digital MOS timing s imulator. The extraction programs make use of an intermediate cir...

This paper introduces performance aspects as a new optimization criteria when generating Gate Matrix Layouts. A new layout model is presented that limits the amount o f parasitic capacitance in signal paths and the resistance in power supply lines. The performance considerations are combined with a new layout s-trate g y that improves circuit performance with little or no area penalty. A n Auto...

This paper introduces performance aspects as a new optimization criteria when generating Gate Matrix Layouts. A new layout model is presented that limits the amount o f parasitic capacitance in signal paths and the resistance in power supply lines. The performance considerations are combined with a new layout s-trate g y that improves circuit performance with little or no area penalty. A n Auto...

System design complexity is growing rapidly. As a result, current development costs can be staggering and are constantly increasing. As designers produce ever larger and more complex systems, it is becoming increasingly difficult to estimate how much time it will take to design and verify these designs. To compound this problem, system design cost estimation still does not have a quantitative a...

We describe a feature-rich conditional random field model for the extraction of conference and workshop information (e.g. name, date, location, deadline) from calls for papers (CFPs). This has applications in the automatic construction of a conference knowledge base from a collection of CFPs. Relevant information in CFPs is often contained in regions that do not contain complete, grammatical se...

Three different techniques for simulating realistic faults generated from IC layout are discussed. Two of them deal with bridging faults, and the third one handles crosstalk faults. The simulation is performed on top of a commercial simulator and thus is very well applicable in an industrial environment. No change of the design database and only minimal changes of the test shell are required. E...

We report an accurate and practical method of estimating interconnect capacitances for a given circuit layout. The method extraction of the complete circuit level capacitances at each node in the circuit. The layout geometry is reduced into base elements that consist of different vertical profiles at each node in the layout. Accurate analytical models are developed for calculating capacitances ...