Our recent results on the demonstration of on-chip mode-division multiplexing functionalities are reviewed, with a special emphasis on the feasibility of nonlinear all-optical signal processing on the silicon-on-insulator (SOI) platform. Mode-selective parametric processes are demonstrated in a 4-mm long SOI waveguide. OCIS codes: (130.3120) Integrated optics devices; (030.4070) Modes; (130.740...

Xiang Zhang and Ahmed Louri Electrical and Computer Engineering, University of Arizona, Tucson, AZ 85721 E-mail:{ zxkidd, louri}@ece.arizona.edu Abstract: We explore silicon photonics and 3D stacked technology to implement a photonic network-on-chips. The proposed scheme provides 2.56 Tb/sec bandwidth with a much reduced power consumption and latency compared to any leading on-chip photonic net...

We describe a compact modulator based on a photonic crystal nanocavity whose resonance is electrically controlled through an integrated p-i-n junction. The sub-micron size of the nanocavity promises very low capacitance, high bandwidth, and efficient on-chip integration in optical interconnects.

We present an optoelectronic-VLSI system that integrates complementary metal-oxide semiconductory multiple-quantum-well smart pixels for high-throughput computation and signal processing. The system uses 5 3 10 cellular smart-pixel arrays with intrachip electrical mesh interconnections and interchip optical point-to-point interconnections. Each smart pixel is a fine grain microprocessor that ex...

In this paper III-V on silicon-on-insulator (SOI) heterogeneous integration is reviewed for the realization of near infrared light sources on a silicon waveguide platform, suitable for inter-chip and intra-chip optical interconnects. Two bonding technologies are used to realize the III-V/SOI integration: one based on molecular wafer bonding and the other based on DVSBCB adhesive wafer bonding. ...

We report an optical link on silicon using micrometer-scale ring-resonator enhanced silicon modulators and waveguide-integrated germanium photodetectors. We show 3 Gbps operation of the link with 0.5 V modulator voltage swing and 1.0 V detector bias. The total energy consumption for such a link is estimated to be approximately 120 fJ/bit. Such a compact and low power monolithic link is an essen...

The microprocessor architecture transition from multi-core to many-core will drive increased chip-to-chip I/O bandwidth demands at processor/memory interfaces and in multi-processor systems. Future architectures will require bandwidths of 200GB/s to 1.0TB/s and will bring about the era of tera-scale computing. To meet these bandwidth demands, traditional electrical interconnect techniques requi...

This paper addresses some fundamental issues relating to the design of systems on chip that utilize optical interconnects. We present an information theoretical model for assessing trade-offs between global and local partitions in these systems, and evaluate interconnect topology synthesis and application mapping techniques for digital signal processing (DSP) applications in these systems.

While serial transceivers move data in and out of an ASIC, on-chip global interconnects move data inside the ASIC. These global interconnects include crossbar switches and busses for sharing on-chip resources. To guarantee quality of service, the on-chip global interconnects are often designed to carry several times worth of traffic compared to the serial transceivers. Close to 10 Tb/s is not a...