in this article, theoretical studies on the selective complexation of the halide ions (f¯, cl¯ and br¯) and ion pairs (na+f¯, na+cl¯ and na+br¯) with the cyclic nano-hexapeptide (cp) composed of l-proline have been performed in the gas phase. in order to calculate the dispersion interaction energies of the cp and ions, dft-d3 calculations at the m05-2x-d3/6-31g(d) level was employed. based on t...

Conventional CMOS charge pump circuits have some current mismatching characteristics. The current mismatch of the charge pump in the PLLs generates a phase offset, which increases spurs in the PLL output signals. In particular, it reduces the locking range in wide range PLLs with a dual loop scheme. A new charge pump circuit with perfect current matching characteristics is proposed. By using an...

In this paper, we introduce a high-speed and low-power Phase-Frequency Detector (PFD) that is designed using a modified TSPC (True Single-Phase Clock) positive edge triggered D flip-flop . The proposed PFD has a simple structure with using only 19 transistors. The operation range of this PFD is over 1.4GHz without using additional prescaler circuits. Furthermore, the PFD has a dead zone less th...

Analog-mixed signal (AMS) circuits are widely used in various mission-critical applications necessitating their formal verification prior to implementation. We consider modeling two AMS circuits as hybrid automata, particularly a charge pump phase-locked loop (CP-PLL) and a full-wave rectifier (FWR). We present executable models for the benchmarks in SpaceEx format, perform reachability analysi...

Positive charge pumps, also known as inductor-less DC/DC converters, are very common in white LED drivers. They are less expensive and simpler to use, but they usually achieve a lower efficiency than inductor-based boost circuits. In this paper, we describe a novel negative charge-pump design for a white LED driver that can automatically select the 1X/1.5X mode. Unlike a conventional positive c...

This paper presents the design of an on-chip charge pump phase-locked loop (CP-PLL) with a fully digital defect-oriented built-in self-test (BIST) for very-high frequency (VHF) applications. The synthesizer has 40–100 MHz tuning range and uses ring voltage-controlled oscillator synthesis. PLL exhibits phase noise −132 dBc/Hz at 1 consumes 1.8 mW on 3 V supply. BIST implementation fewer external...

A PLL circuit includes phase detector for detecting phase error between an input and output signal of the PLL circuit and outputting pump up and pump down signal. A charge pump generates a charge pump signal in response to pump up and pump down signals. A loop filter filters charge pump signal to generate a filtered signal. A boost-up device coupled to loop filter output terminal charges a loop...

To dramatically reduce the need for Silicon frequency synthesizer is always measured in integer mode reproduction due to poor noise performance, a close-loop first and then measured in fractional mode. The fractional simulation platform that combines both measured and/or mode would yield the same phase noise performance when simulation results of open-loop PLL sub-blocks has been compared to th...

In this article a novel charge pump circuit is introduced. The proposed circuit utilizes a bulk driven cascode current mirror through an adaptive gate bias technique, that results in a high output impedance over a very wide output voltage range, accurate Charge/ Discharge current matching, which minimizes the steady-state phase error in a phase-locked loop (PLL), and low transient glitches. The...

A low-power wideband self-biased phase-locked loop (SPLL) is proposed for multi-protocol SerDes applications in this letter. With the adaptive fast-locking current circuit (AFLCC) and charge pump (CP), settling time reduced significantly, no extra power jitter contribution. In addition, a start-up module adopted to reset system an optimal initial operating frequency quickly. The 1-3-GHz SPLL, f...