A linear capacitor structure using fractal geometries is described. This capacitor exploits both lateral and vertical electric fields to increase the capacitance per unit area. Compared to standard parallel-plate capacitors, the parasitic bottomplate capacitance is reduced. Unlike conventional metal-to-metal capacitors, the capacitance density increases with technology scaling. A classic fracta...

 Liquid impedance measurements based on capacitive (or contactless) electrodes overcome electrode polarization problems but are affected by stray capacitance from the material being measured to ground, the same as measurements with direct-contact electrodes. This study shows that the effects of that capacitance depend on the impedance being measured and for bipolar impedance measurements they ...

In the current study, stress-induced capacitance determined by direct measurement on MOSFETs was compared with that determined by indirect simulation through the delay of CMOS ring oscillators (ROs) fabricated side by side with MOSFETs. External compressive stresses were applied on 〈110〉 silicon-on-insulator (SOI) n-/p-MOSFETs with the ROs in a longitudinal configuration. The measured gate capa...

With the smaller layout area and parasitic capacitance under the same electrostatic discharge (ESD) robustness, silicon-controlled rectifier (SCR) has been used as an effective on-chip ESD protection device in radio-frequency (RF) IC. In this paper, SCR's with the waffle layout structures are studied to minimize the parasitic capacitance and the variation of the parasitic capacitance within ult...

A circuit for capacitance measurements is described. The circuit permits offset capacitance compensation using a dc voltage. The electronic circuitry with its testing is described. The output voltage is a linear function of the capacitance measured. Experimental data show good agreement with values predicted by the linear formula. Experiments show it is possible to measure capacitance changes w...

To mitigate the radio-frequency (RF) performance degradation caused by electrostatic discharge (ESD) protection device, low capacitance (low-C) design on ESD protection device is a solution. With the smaller layout area and small parasitic capacitance under the same ESD robustness, silicon-controlled rectifier (SCR) device has been used as an effective on-chip ESD protection device in RF ICs. I...

Bulk and novel MOSFET structures with gate-lengths in the 30nm regime are expected to become industry standards in ~2007. As devices are scaled down to these lengths, overlapand fringe-capacitance between the gate and source/drain regions gain more importance as a fraction of the total gate-capacitance. Therefore in numerical simulations of these structures it is necessary to carefully include ...

This paper investigates the design curves of class E amplifier with nonlinear capacitance for any output Q and finite dc-feed inductance. The important results are; 1) the capacitance nonlinearity strongly affects the design parameters for low Q, 2) the value of dc-feed inductance is hardly affected by the capacitance nonlinearity, and 3) the input voltage is an important parameter to design cl...

In mixed circuit simulation, the estimation of parasitic capacitances of deep-submicron MOSFETs is very important. With the continuous scaling of the devices, the extrinsic capacitance, i.e. the overlap and fringing capacitances become a growing fraction of the total gate capacitance. We found the major existing models do not predict correctly the overlap capacitance and the inner fringing capa...

The e!ect of interconnect coupling capacitance on the transient characteristics of a CMOS logic gate strongly depends upon the signal activity. A transient analysis of CMOS logic gates driving two and three coupled resistive}capacitive interconnect lines is presented in this paper for di!erent signal combinations. Analytical expressions characterizing the output voltage and the propagation dela...