Branch prediction accuracies determined using tracedriven simulation do not include the eflects of executing branches along a mispredicted path. However, branches along a mispredicted path will pollute the branch prediction structures i f no recovery mechanisms are provided. Without recovery mechanisms, prediction rates will suger. In this paper, we determine the appropriateness of recovery mec...

Branch Prediction is a common function in nowadays microprocessor. Branch predictor is duplicated into multiple copies in each core of a multicore and many-core processor and makes prediction for multiple concurrent running programs respectively. To evaluate the parallel branch prediction in many-core processor, existed schemes generally use a parallel simulator running in CPU which does not ha...

This paper discusses the effects of using a trace cache on the indirect branch prediction in ILP processors. The main contribution of the paper is an exploration of the fact that the trace cache captures context information about the recent control flow of the program, which can improve the accuracy of predictors that do not themselves explicitly use such information. We analyze and experiment ...

In order to meet high performance demands, modern processor architectures exploit varieties of dynamic branch prediction topologies ([4]-[6] provide an excellent introduction and research coverage) to increase instruction-level parallelism (ILP). Dynamic branch predictors use run-time branch execution history to predict branch direction. Most previous techniques use a branch pattern history tab...

Energy-efficient dynamic branch predictors are proposed for the Cell SPE, which normally depends on compiler-inserted hint instructions to predict branches. All designed schemes use a Branch Target Buffer (BTB) to store the branch target address and the prediction, which is computed using a bimodal counter. One prediction scheme predecodes instructions when they are fetched from the local store...

Indirect branch targets are hard to predict as there may be multiple targets corresponding to a single indirect branch instruction. Value Based BTB Indexing (VBBI), a recently proposed indirect branch prediction technique, utilizes the compiler to identify a ‘hint instruction’, whose output value strongly correlates with the target address of an indirect branch. At run time, multiple targets ar...

Predicated Execution can be used to alleviate the costs associated with frequently mispredicted branches. This is accomplished by trading the cost of a mispredicted branch for execution of both paths following the conditional branch. In this paper we examine two enhancements for branch prediction in the presence of predicated code. Both of the techniques use recently calculated predicate defini...

Taking advantage of instruction level parallelism is one of the key factors in improving computer performance. The main performance inhibitor in a pipelined processor is the branch penalty. Many techniques have been developed to reduce this penalty. The technique of branch prediction was explored further. Branch predictors are crucial in today's modern, superscalar processors for achieving high...

We propose an enhanced multiple branch predictor using per-primary address branch histories. Using this scheme, the interferences among diierent branches are reduced, enhancing the average prediction accuracy. Also, since the branches predicted each cycle do not suuer from successive dependencies, predictions are generated in parallel. This scheme results in higher average branch prediction acc...

The importance of accurate branch prediction to future processors has been widely recognized. The correct prediction of conditional branch outcomes can help avoid pipeline bubbles and attendant loss in performance. In order to achieve high prediction accuracy, numerous dynamic branch prediction schemes that exploit branch correlation have recently been proposed. Several of the best predictors a...