A complementary gallium-arsenide (CGaAs) 53-bit parallel array floating point multiplier is presented. The design uses Motorola's 0.5µm C-GaAs process. A conventional Wallace tree of 42 compressors is used to generate the product terms and a dynamic Ling carry select adder is utilized in the final addition to form the final mantissa. An internal latch allows the design to use a two cycle pipeli...

The JPEG 2000 image compression standard is designed for a broad range of data compression applications. The Discrete Wavelet Transformation (DWT) is central to the signal analysis and is important in JPEG 2000 and is quite susceptible to computer-induced errors. However, advancements in Field Programmable Gate Arrays (FPGAs) provide a new vital option for the efficient implementation of DSP al...

Representing finite field elements with respect to the polynomial (or standard) basis, we consider a bit parallel multiplier architecture for the finite field GF (2). Time and space complexities of such a multiplier heavily depend on the field defining irreducible polynomials. Based on a number of important classes of irreducible polynomials, we give exact complexity analyses of the multiplier ...

In this paper, we propose an MSD (most significant digit) multiplier based on an MSB (most significant bit) multiplier over GF(2). The proposed multiplier is based on connecting D (digit size)-bit bit-operations in series. In each digit operation in our proposed multiplier, the “left shift and reduction operation” is serially performed for each of D bits. Because registers for storing intermedi...

The multiplier and multiplier-and-accumulator (MAC) are the essential elements of the digital signal processing. Multiplication involves two basic operations: the generation of partial products and their accumulation. Partial products can be reduced by using the Radix_4 modified Booth algorithm. The design of a binary signed-digit partial product generator, which expresses each normal binary op...

The paper presents a new multiplier enabling achievement of an arbitrary accuracy. It follows the same idea of number representation as the Mitchell’s algorithm, but does not use logarithm approximation. The proposed iterative algorithm is simple and efficient and its error percentage is as small as required. As its hardware solution involves adders and shifters, it is not gate and power consum...

In this paper, we present a new efficient distributed arithmetic (NEDA) formulation of the computation of 1-D discrete wavelet transform (DWT) using 9/7 filters, and mapped that into bit parallel for high-speed and low hardware implementations, respectively. We demonstrate that NEDA is a very efficient architecture with adders as the main component and free of ROM, multiplication, and subtracti...

AbstractIn this work faster column compression multiplication has been achieved by using a combination of two design techniques: partition of the partial products into two parts for independent parallel column compression and acceleration of the final addition using a hybrid adder proposed in this work. Based on the proposed techniques 8, 16, 32 and 64bit Dadda multipliers are developed and com...

In this paper an algorithm for GF(2") multiplication/division is presented and a new, more generalized definition of duality is proposed. From these the bit-serial Berlekamp multiplier is derived and shown to be a specific case of a more general class of multipliers. Furthermore, it is shown that hardware efficient, bit-parallel dual basis multipliers can also be designed. These multipliers hav...

Two’s complement multipliers are important for a wide range of applications. Paper describes a technique to reduce by one row the maximum height of the partial product array generated by Radix-4 Booth’s multiplier, without any increase in the delay of the partial product generation stage. The design of 8 bit and 16 bit multiplication scheme using different types of multiplier like Array multipl...