A new performance and area optimization algorithm for complex VLSI systems is presented. It is widely believed within the VLSI CAD community that the relationship between delay and silicon area of a VLSI chip is convex. This conclusion is based on a simpliied linear RC model to predict gate delays. In the proposed optimization algorithm, a nonlinear, non-RC based transistor delay model was used...

Column-convex polygons were first counted by area several decades ago, and the result was found to be a simple, rational, generating function. In this work we generalize that result. Let a p-column polyomino be a polyomino whose columns can have 1, 2, . . . , p connected components. Then columnconvex polygons are equivalent to 1-convex polyominoes. The area generating function of even the simpl...