This paper enumerates a low power, high speed design of flip-flop having less number of transistors. In flip-flop design only one transistor is being clocked by short pulse train which is known as True Single Phase Clocking (TSPC) flip-flop. The true single-phase clock (TSPC) is common dynamic flip-flop which performs the flip-flop operation with little power and at high speeds. In this paper, ...

The paper presents the concept of existing D fuzzy flip-flop design and analyses the working of the design. The existing design has been studied for its delay parameters and variability. Comparisons with the previous designs has been done to lay down the superiority of the fuzzy design over existing binary flip-flop designs. Keywords— Binary flip-flop, Fuzzy flip-flop, D fuzzy flip-flop, delay,...

The paper proposed a new design for implementing a Single Edge Triggered Flip-Flop. In this work, comparative analysis of six existing flip-flop designs along with the proposed design is made. In the proposed design the number of clocked transistors is reduced to decrease the power consumption and it also employs the conditional feedback to reduce the short-circuit currents. All simulations are...

Abstract Quantum-dot cellular automata (QCA) is a likely candidate for future low power nano-scale electronic devices. Sequential circuits in QCA attract more attention due to its numerous application in digital industry. On the other hand, configurable devices provide low device cost and efficient utilization of device area. Since the fundamental building block of any sequential logic circuit ...

The logic construction of a double-edge-triggered (DET) flip-flop, which can receive input signal at two levels of the clock, is analyzed and a new circuit design of CMOS DET flip-flop is proposed. Simulation using SPICE and a 1 micron technology shows that this DET flip-flop has ideal logic functionality, a simpler structure, lower delay time and higher maximum data rate compared to other exis...

Deriving a dynamic model based on the coupled-mode and carrier rate equations, the effects of coupling coefficient and corrugation position on all-optical flip-flops (AOFF) we have analyzed in this paper. Also the self phase modulation (SPM) in the distributed coupling coefficient distributed feedback semiconductor optical amplifier (DCCDFB-SOA) has been implemented. Then the effects of SPM on ...

The logic construction of a double-edge-triggered (DET) flip-flop, which can receive input signal at two levels of the clock, is analyzed and a new circuit design of CMOS DET flip-flop is proposed. Simulation using SPICE and a 1μ technology shows that this DET flip-flop has ideal logic functionality, a simpler structure, lower delay time, and higher maximum data rate compared to other existing ...