This paper describes a hardware accelerator for elliptic curve cryptography. The accelerator performs Galois field operations as a series of microcode instructions operating on 32-bit subsections of operands, which represent elements from GF(2) in a binary polynomial basis. The accelerator may be used for arbitrary size elliptic curves up to a field degree of 512. Parallelism between operations...

Being an integral part of accelerator software, accelerator description aims to provide an external representation of an accelerator’s internal model and associative effects. As a result, the choice of description formats is driven by the scope of accelerator applications and is usually implemented as a tradeoff between various requirements: completeness and extensibility, user and developer or...

This paper presents an accelerator for k-th nearest neighbor thinning, a run time intensive algorithmic kernel used in recent multi-objective optimizers. We discuss the thinning algorithm and the accelerator architecture with its modules and operation, and evaluate the accelerator with respect to two different application scenarios. The first is an embedded computing scenario where the accelera...

The Unified Accelerator Libraries[1] are designed as a customizable and extendible environment for developing diverse accelerator applications. Its main architectural principle is a separation of physical entities and mathematical abstractions from algorithms. The accelerator algorithms are implemented as classes that share data via Common Accelerator Objects (Element, Bunch, Twiss, etc.). This...

An overview of the framework of Unified Accelerator Libraries (UAL) is presented. The UAL framework is a necessary and logical step in the UAL evolution. It intends to offer a standard-based infrastructure that facilitates compatible and independent implementation of accelerator applications and the development of interoperable Accelerator Simulation Facilities. The paper explain the two major ...

We present a flexible accelerator designed for networking applications. The accelerator can be utilized efficiently by a variety of Network Processor designs. Many Network Processors employ hardware accelerators for implementing key domain-specific tasks. New applications require new tasks, such as pattern matching, to be performed on network packets in real-time. Using our proposed accelerator...