The gate-oxide (aka gate tunneling or gate) leakage due to quantum-mechanical direct tunneling of carriers across the gate dielectric of a device is a major source power dissipation for sub-65nm CMOS circuits. In this paper a high-level (aka architecture) synthesis algorithm is presented that simultaneously schedules operations and binds to modules for gate leakage optimization. The algorithm u...

In this paper different low power 8x8 bit multipliers which are implemented with Tanner Tool v13.0 at 250MHz and 500MHz frequency with 65nm technology which is having a supply voltage 1.0v. There are different CMOS multiplier circuits are analyzed which are Array multiplier, Wallace tree multiplier, Row bypass Braun multiplier, Column bypass Braun multiplier, Row and Column bypass Braun multipl...

On chip testing is an attractive solution for testing of analog integrated circuits. In this paper a low power , built in CMOS Ripple Detector is presented for the purpose of detecting the ripples in the supply rails and specifies its application for On chip testing. The detector works on the principle of RMS detection. The circuit outputs a DC signal that is proportional to the peak to peak am...

Ultra-low power (ULP) biomedical implants and sensor nodes typically require small memories of a few kb, while previous work on reliable subthreshold (sub-VT) memories targets several hundreds of kb. Standard-cell based memories (SCMs) are a straightforward approach to realize robust subVT storage arrays and fill the gap of missing sub-VT memory compilers. This paper presents an ultra-low-leaka...

The leakage power dissipation problem of electronics systems has attracted a lot of attention from engineers and researchers over the years. Increasing leakage current in deep-sub micrometer regimes is becoming a significant contributor to power dissipation of CMOS circuits as threshold voltage, channel length, and gate oxide thickness are reduced. Consequently, the identification and modeling ...

A standard cell based gate level synchronous full adder design is presented in this paper. The main highlight of the article is that the proposed full adder realization is found to be better in terms of power-delay product (PDP), even in comparison with the full adder element that has been made available as part of two commercial standard cell libraries viz. the high-speed 130nm Faraday (UMC) b...

Current mode circuits like current conveyors are getting significant attention in current analog ICs design due to their higher band-width, greater linearity, larger dynamic range, simpler circuitry, lower power consumption and less chip area. The second generation current controlled conveyor (CCCII) has the advantage of electronic adjustability over the CCII i.e. in CCCII; adjustment of the X-...

Current mode circuits like current conveyors are getting significant attention in current analog ICs design due to their higher band-width, greater linearity, larger dynamic range, simpler circuitry, lower power consumption and less chip area. The second generation current controlled conveyor (CCCII) has the advantage of electronic adjustability over the CCII i.e. in CCCII; adjustment of the X-...

In this research a new design of the transimpedance amplifier (TIA) with current mirror was employed by technique (65nm). The TIA consists common gate transistor (CG TIA) and source as an input stage local active feedback second to increase gain. order verify performance proposed TIA, circuit simulation carried out in LT spice program using coefficients (65nm CMOS). results indicate that interf...