Resumo. Organizações têm sido cobradas por sua capacidade de fornecer informações sobre seu funcionamento e resultados. Porém tornar-se transparentes não é apenas divulgar informações, é necessário que estas informações sejam tratadas, usadas e compreendidas por seu público alvo. Este artigo descreve uma proposta de evolução de um Catálogo de Transparência, com um estudo mais aprofundado sobre ...

With the continued shrinking of CMOS technologies and smaller device sizes, soft errors have become of major concern. Since these types of errors do not reflect a permanent failure of the device, they are also called transient faults. Transient faults or soft errors are mainly caused by Single Event Upsets (SEUs). SEU is a bit-flip in digital systems due to the impact of energy particles [17]. ...

The total dose effects and SEEs of RT54SX, a new radiation tolerant antifuse FPGA family, are presented. This device family employs a metal-to-metal antifuse technology and a sea-of-modules architecture. Devices manufactured by both 0.6 μm and 0.25 μm technology levels are tested. The devices demonstrate the total dose tolerance better than 100 krad(Si). They are SEL and SEDR immune. For SEU, 0...

Larger field programmable gate array (FPGA) configuration memories and shrinking design rules have raised concerns about single event upsets (SEUs), especially for highreliability, high-availability systems that use FPGAs. We present a design for the on-line detection and correction of SEUs in the configuration memory of Xilinx Virtex-4 and Virtex-5 FPGAs. The design corrects all single-bit err...

Subjective expected utility (SEU) rests on and implies four tenets of rational preferences; transitivity, monotonicity of consequences, independence of a common consequence, and accounting equivalences. Empirical evidence against transitivity and monotonicity is reevaluated and the opposite conclusion drawn using more recent data. The more complex accounting equivalences are descriptively impla...

The benefits of FPGAs over ASICs become ever more compelling as rapid-process technology scaling and innovation provide ever-greater speed, density, and power improvements. However, along with technology scaling come other effects that previously could be ignored. One of the accompanying effects is increased susceptibility to soft errors caused by single event upsets (SEUs). Although through ca...

This paper describes software fault tolerance techniques to mitigate SEU faults in the Raw architecture, which is a single-chip parallel tiled computing architecture. The fault tolerance techniques we use are efficient Checkpointing and Rollback of processor state, Break-pointing, Selective Replication of code and Selective Duplication of tiles. Our fault tolerance techniques can be fully imple...

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