We present a new technique for generating compact dictionaries for cause-effect diagnosis in BIST. This approach relies on the use of three compact dictionaries: (i) D1, containing compacted LFSR signatures for a small number of patterns and faults with high detection probability, (ii) an interval-based pass/fail dictionary D2 for the BIST patterns and for faults with relatively lower detection...

In a random testing environment, a significant amount of energy is wasted in the LFSR and in the CUT by useless patterns that do not contribute to fault dropping. Another major source of energy drainage is the loss due to random switching activity in the CUT and in the scan path between applications of two successive vectors. In this work, a new built-in self-test (BIST) scheme for scan-based c...

In order to reduce key sizes and bandwidth, cryptographic systems have been proposed using minimal polynomials to represent finite field elements. These systems are essentially equivalent to systems based on characteristic sequences generated by a linear feedback shift register (LFSR). We propose a general class of LFSR-based key agreement and signature schemes based on n-th order characteristi...

Power consumption for test vectors is a major problem in SOC testing using BIST. A new low power testing methodology to reduce the peak power and average power associated with scan-based designs in the deterministic BIST is proposed. This new method utilizes an auxiliary LFSR to reduce the amount of the switching activity in the deterministic BIST. Excessive transition detector (ETD) monitors t...

Most approaches to the synthesis of built-in self test (BIST) circuitry use a manual choose-and-evaluate approach, where a particular BIST generator is chosen and then evaluated by faultsimulating the design with the vectors that the chosen generator generates. We develop an algorithmic synthesis-during-test approach in this paper, wherein the tasks of synthesizing the BIST logic and directed t...

When using Built-In Self Test (BIST) for testing VLSI circuits the circuit response to an input test sequence, which may consist of thousands to millions of bits, is compacted into a signature which consists of only tens of bits. Usually a linear feedback shift register (LFSR) is used for response compaction via polynomial division. The compacting function is a many-to-one function and as a res...

In verifiable multi-secret sharing schemes (VMSSs), many secrets can be shared but only one share is kept by each user and this share is verifiable by others. In this paper, we propose two secure, efficient, and verifiable (t, n) multi-secret sharing schemes, namely Scheme-I and Scheme-II. Scheme-I is based on the Lagrange interpolating polynomial and the LFSR-based public key cryptosystem. The...

Recent strides in programmable logic density, speed and hardware description language (HDL) have empowered the engineer with the ability to implement high-performance digital functionality within field programmable gate array (FPGA). Linear feedback shift resister (LFSR) has become one of the central elements used in testing and self testing of contemporary complex electronic systems like proce...

Pseudo-random number generation on the Atari 2600 was commonly accomplished using a Linear Feedback Shift Register (LFSR). One drawback was that the initial seed for the LFSR had to be hard-coded into the ROM. To overcome this constraint, programmers sampled from the LFSR once per frame, including title and end screens. Since a human player will have some random amount of delay between seeing t...