This work introduces the use of GradedChannel SOI MOSFETs to make analog current mirrors and compare their performance with those made with conventional fully depleted SOI transistors. It is demonstrated that Graded-Channel MOSFETs can provide higher precision current mirror with enhanced output swing. Also lesser modifications of the output characteristics due to the self-heating effect than i...

A current-mode output driver that supports SERDES applications is implemented using 0.13 μm Bulk and PD SOI CMOS technologies. Schematic simulation results confirm the enhanced performance of PD SOI for very high-speed interfaces. The PD SOI current-mode driver shows a 3 times lower data dependent jitter than the Bulk current-mode driver at the same 3.125 Gbps data rate of XAUI standard.

The authors report a 0.7V Manchester carry look-ahead circuit using partially depleted (PD) SOI CMOS dynamic threshold (DTMOS) techniques for low-voltage CMOS VLSI systems. Using an asymmetrical dynamic threshold pass-transistor technique with the PD-SOI DTMOS dynamic logic circuit, this 0.7V PD-SOI DTMOS Manchester carry look-ahead circuit has an improvement of 30% in propagation delay time co...

SOI technology has received high attention for the future high density DRAM applications. The two major requirements in any DRAM technology are long retention time and high charging efficiency. This paper discusses the disadvantages of using bulk silicon and Partially Depleted SOI devices in these terms. It is shown that a DRAM cell built with fully depleted SOI MOSFETs can store data for a lon...

A new small-signal model for fully depleted silicon-oninsulator (FD-SOI) MOSFETs operating at RF frequencies is presented. The model accounts for the non-quasi-static effect by determining model parameters using a curve fitting procedure to reproduce the frequency response of FD-SOI MOSFETs. The accuracy of the model is validated by comparison of S parameters with measured results in the range ...

We present a silicon-on-insulator (SOI) pass-transistor logic (PTL) gate with an active body bias control circuit and compare the proposed PTL gate with other types of PTL gates with different body bias circuits in two different 0.13μm SOI CMOS technologies. The experimental results show that the proposed SOI PTL gate using the body bias controlled technique is superior in terms of performance ...

This paper describes 0.18um CMOS silicon-on-insulator (SOI) technology and design techniques for SOI RF switch designs for wireless applications. The measured results of SP4T (single pole four throw) and SP8T (single pole eight throw) switch reference designs are presented. It has been demonstrated that SOI RF switch performance, in terms of power handling, linearity, insertion loss and isolati...

VLSI technology is being driven to giga-scale levels of integration with IC minimum feature dimensions approaching atomic scales. System-level integration is now pursued as critical in major commercial applications including wireless communication, computing, and multimedia. On-chip signal integrity, noise, and electromagnetic compliance (EMC) are becoming “showstoppers” in addition to escalati...