A wideband CMOS variable gain low noise amplifier suitable for multi-standard radio applications between 75 MHz and 3 GHz is presented. Wideband matching to 50 Ohm (single ended) is achieved using a common-drain feedback stage whereas variable gain is realized using a resistive attenuator. The circuit has been designed in a 65 nm CMOS process and achieves 22 dB maximum gain, 29 dB gain range, 3...

A harmonic mixer for direct-conversion receivers is proposed and fabricated in a CMOS process. It is immune from both the flicker noise and self-mixing induced DC offset. Using the lateral bipolar transistor and the harmonic mixing technique, it achieves +15dB gain, 17.8dB NF at 10kHz frequency, 8.2dBm IIP3, +44dBm IIP2 and more than 30dB DC offset suppression. It consumes 2.2mW power at 3V.

This paper describes a 1.5-V 2.4-GHz silicon down conversion mixer with a CMOS gm Cell using 0.35 um process [1]. With a 2.3-GHz local oscillator (LO) and a 2.4-GHz RF input, the mixer minimum double sideband noise figure (DSB NF) is 8.9 dB. The input third-order intercept point (IIP3) is 0.5 dBm, and the power conversion gain is 18 dB.

A 1.9 GHz (RF) down conversion mixer has been designed in a standard 0.25μ CMOS process. The local oscillator (LO) frequency is at 1.85 GHz. The mixer provides a voltage gain of 2.133 dB while drawing a current of 5.2 mA from a 2.5 V supply. The IIP3 of the mixer is 5.123 dBm and the -1dB compression is at -5.83 dBm. Detailed design process and simulation results are presented in this report.

A discrete-time mixing architecture for software defined radio receivers is proposed. It exploits 8x RF voltage oversampling followed by charge domain weighting to achieve 40dB 3rd and 5th harmonic rejection without channel bandwidth limitations. Also noise folding is reduced by 3dB. A zero-IF downconverter chip in 65nm CMOS can receive RF signals up to 900MHz, with NFmin=12dB, IIP3=11dBm at <2...

This paper proposes a wideband common-gate LNA using capacitive feedback. The transconductance of the proposed LNA can be enlarged and noise figure can be improved while the conventional common-gate LNA has to use a smaller transconductance for the input impedance matching. In the experimental results using a 0.18-μm CMOS technology, the gain is 13.4 dB, NF is 2.7 dB, IIP3 is −7 dBm at 0.8GHz, ...

In this paper presents a optimization of linearity of low noise amplifier by using post linearization techniques. in this technique we have used diode connected mosfet as IMD sinker also used interstage matching for gain enhancement and reducing the effect of nonlinearity in common gate stage of cascode amplifier, this has done by using UMC .18um CMOS Technology in cadence tool. We got gain 14d...

In this paper, we present the low noise amplifier using new feedback connection configurations. The UWB LNA is design in 0.18 m TSMC CMOS technique to achieve high gain, small size and low noise. The LNA achieved 11 dB of average power gain, low 2.87 dB noise figure (NF), -10.9 dB input match, -7 dB return loss, -3 dBm of IIP3 and only 0.54 mm size with 15 mW power consumption.

This paper describes a 1.5-V 5 GHz I/Q down conversion mixer in a 0.18-μm CMOS process. The mixer achieves a conversion gain of 12.7 dB within 1-dB compression point (iCP1dB) of -15.83 dBm. It also achieves a double side band (DSB) NF of 13.5 dB. The mixer's IIP3 is -5.94 dBm. The mixer consumes only 5.72 mA of current from a 1.5-V power supply. Key-Words: Analog RF-CMOS, IEEE 802.11a, IEEE 802...

A widely tunable 4th order BPF based on the subtraction of two 2nd order 4-path passive-mixer filters with slightly different center frequencies is proposed. The center frequency of each 4-path filter is slightly shifted relative to its clock frequency (one upward and the other one downward) by a gm-C technique. Capacitive splitting of the input signal is used to reduce the mutual loading of th...