Sub-threshold leakage and process-induced variations in bulk-Si technology limit the scaling of SRAM into sub-32 nm nodes. New device architectures are being considered to improve control Vt and reduce short channel effects. Among the likely candidates, FinFETs are the most attractive option because of their good scalability and possibilities for further SRAM performance and yield enhancement t...

Due to continuous scaling of CMOS, stability is a prime concerned for CMOS SRAM memory cells. As scaling will increase the packing density but at the same time it is affecting the stability which leads to write failures and read disturbs of the conventional 6T SRAM cell. To increase the stability of the cell various SRAM cell topologies has been introduced, 8T SRAM is one of them but it has its...

As the technology is improving , channel length of MOSFET is scaling down. In this environment stability of SRAM becomes the major concern for future technology. Static noise margin (SNM)[1] plays a vital role in stability of SRAM[2]. This paper gives an introduction to the “8T SRAM cell”[3]. It includes the Implementation, characterization and analysis of 8T SRAM cell and its comparison with t...

As modern technology is spreading fast, it is very important to design low power, high performance, fast responding SRAM(Static Random Access Memory) since they are critical component in high performance processors. In this paper we discuss about the noise effect of different SRAM circuits during read operation which hinders the stability of the SRAM cell. This paper also represents a modified ...

This paper addresses a, novel eight transistor (8T) CMOS SRAM cell design to enhance the stability and to reduce dynamic and leakage power. For the validation of proposed 8T SRAM cell, compared results with reported data. The parameters used in the proposed cell are comparable to the existing 8T SRAM cell at same technology and design rules. The stability of the proposed cell has been analyzed ...

Memories are a core part of most of the electronic systems. Performance in terms of speed and power dissipation is the major areas of concern in today’s memory technology. In this paper SRAM cells based on 6T, 7T, 8T, and 9T configurations are compared on the basis of performance for read and write operations. Studied results show that the power dissipation in 7T SRAM cell is least among other ...

For super-parallel video processing, we proposed a powerand area-efficient SRAM core architecture with a segmentation-free access, which means accessibility to arbitrary consecutive pixels, and horizontal/vertical access. To achieve these flexible accesses, a spirallyconnected local-wordline select signal and multi-selection scheme in wordlines are proposed, so that extra X-decoders in the conv...

Present day electronic industry faces the major problem of standby leakage current, as the processor speed increases, there is requirement of high speed cache memory. SRAM being mainly used for cache memory design, several low power techniques are being used for SRAM cell design. Full CMOS 6T SRAM cell is the most preferred choice for digital circuits. This paper reviews various leakage power t...

In this paper a new 7T SRAM is proposed. CMOS SRAM Cell is very less power consuming and have very less read and write time. In proposed SRAM an additional write bit line balancing circuitry is added in 6T SRAM for power reduction. A seven Transistor (7T) cell at 45 nm Technology is proposed to accomplish improvement in stability, power dissipation and performance compared with previous designs...

In this paper, a new write assist technique for SRAM arrays is proposed. In this technique, to improve the write features of the SRAM cell, a negative voltage is applied to one of the bitlines in the SRAM cell while another bitline is connected to a boosted voltage. Improved write features are attributed to the boosting scheme from both sides of the SRAM cell. This technique is applied to a 10T...