Enhancing the Performance and Fairness of Shared DRAM Systems with Parallelism-Aware Batch Scheduling Onur Mutlu Thomas Moscibroda Microsoft Research Abstract In a chip-multiprocessor (CMP) system, the DRAM system is shared among cores. In a shared DRAM system, requests from a thread can not only delay requests from other threads by causing bank/bus/row-buffer conflicts but they can also destro...

Sapphire is a multi-processor/multicore simulator where the memory hierarchy, interconnect (network on chip) and offchip DRAM are parametrized and can be configured to model various configurations. Sapphire addresses shortcomings in SESC by integrating it with Ruby from the GEMS framework. Sapphire also integrates Intacte, an interconnect power model. DRAMSim models off-chip DRAM in great detai...

The larger volume of capacitor and higher leakage current of transistor have become the inherent disadvantages for the traditional one transistor (1T)-one capacitor (1C) dynamic random access memory (DRAM). Recently, the tunneling FET (TFET) is applied in DRAM cell due to the low off-state current and high switching ratio. The dual-gate TFET (DG-TFET) DRAM cell with the capacitorless structure ...

Emerging portable devices relay on DRAM/flash memory system to satisfy requirements on fast and large data storage and low-energy consumption. This paper presents a novel approach to reduce energy of memory system, which unlike others, lowers energy of refresh operation in DRAM. The approach is based on two key ideas: (1) DRAM-based flash cache that keeps dirty pages to reduce the number of acc...

Main memory system design and corresponding technology requirements have become increasingly challenging for data-dominated high-performance applications. To address the leakage scalability issues of conventional DRAM-based memory, new technologies with ultra-low potential high been explored extensively over last decade. However, none them are mature enough to serve as a drop-in replacement DRA...

In the arsenal of resources for computer memory system performance improvement, predictors have gained an increasing role in the past years. They can suppress the latencies when accessing cache or main memory. In paper [1] it is shown how temporal parameters of cache memory access, defined as live time, dead time and access interval could be used for prediction of data prefetching. This paper e...

DRAM requires periodic refresh to prevent data loss from charge leakage. There exists two main refresh methods employed in the majority of today’s DRAM systems. The first method is to carry out refresh operations at the rank level, called all-bank refresh (REFab), which is mainly used by commodity DDR DRAM [6]. Because all-bank refresh prevents all banks within an entire DRAM rank from serving ...