This paper investigates the use of carbon nanotube field effect transistors (CNFETs) for the design of ternary full adder cells. The proposed circuits have been designed based on the unique properties of CNFETs such as having desired threshold voltages by adjusting diameter of the CNFETs gate nanotubes. The proposed circuits are examined using HSPICE simulator with the standard 32 nm CNFET tech...

This paper deals with the propagation delay comparison of half adder with different FETs; such as MOSFET, CNTFET, FINFET. Nanotechnology is the promising field which functions at the molecular level to replace the conventional use of classical CMOS. By simulation, the best part is got that CNTFET shows lesser delay for half adder circuit.

Skyrmion-based devices are promising candidates for non-volatile memory and low-delay time computation. Many skyrmion-based execute operation by controlling skyrmion trajectory, which can be impeded the Hall effect. Here, design of arithmetic built on synthetic antiferromagnetic (SyAF) structures is presented, where structure greatly suppress In this study, operations half adder, full XOR logic...

Adders is widely used in applications such as digital signal processing (DSP) and microprocessors. In this paper Half adders are simulated and analyzed based on power dissipation, area and speed on 90nm technology using Microwind and Dsch tool. Half Adder is the basic building block in Parallel Feedback Carry Adder (PFCA).

With the rapid development of modern computers, problems caused by performance gap between processor and memory in von-Neumann architecture have become significant. Spintronic devices, benefitting from potential achieving in-memory computing, one most competitive candidates to bridge gap. Great efforts been made realize functions computers using spintronic devices. Here, a nonvolatile magnetic ...

Multiple-Valued Logic systems present significant improvements in terms of energy consumption over binary logic systems. This paper proposes new ternary combinational digital circuits that reduce low-power nano-scale embedded and Internet Thing (IoT) devices to save their battery consumption. The 32 nm CNTFET-based half adder (THA) multiplier (TMUL) use novel unary operator implement two power ...