The main issue in VLSI design are optimizing speed, scaling in silicon technology and increased packing density. These issues account for increased power dissipation in SoC (System on Chips) making them unsuitable for portable operations. Since SRAM consist of almost 60% of VLSI circuits, hence, it is needed that a low power SRAM design to maximize the run time with minimum requirements on size...

In this paper we have analyzed the advantages of using dynamic circuits over static circuits with result oriented example for NAND operation. The different aspects covered under this discussion include power, speed, area, input Capacitance and timing delays calculation. We have also covered the problem of increase in dynamic power dissipation at the dynamic and the output node in dynamic circui...

From the last few decades, the scaling down of CMOS devices have been taking place to achieve better performance in terms of speed, power dissipation, size and reliability. The major area of concern in today‟s CMOS technology is Data retention and leakage current reduction. SRAM (Static Random Access Memory) is memory used to store data. Conventional Static Random Access Memory (SRAM) cells suf...

This paper presents a new quasi adiabatic logic family that uses a pair of complementary split-level sinusoidal power supply clocks for digital low power applications such as sensors. The proposed two phase clocked adiabatic static CMOS logic (2PASCL) circuit utilizes the principle of adiabatic switching and energy recovery. By removing the diode at the charging path, higher output amplitude is...

This paper proposes a new quasi adiabatic logic family that uses two complementary pulsed supply clock for digital low power applications such as sensors. The proposed two-phase adiabatic static CMOS logic circuit (2PASCL) has switching activity that is lower than dynamic logic and can be directly derived from static CMOS circuits. We have done a SPICE simulation on the chain of four 2PASCL inv...

One of the principal economic drivers for the semiconductor industry is high performance, low power applications for the portable electronics consumer market. Unfortunately, the power dissipation resulting from the use of conventional CMOS technology in this area is becoming a critical design issue. Supply voltage reduction has been the preferred technique for reducing power dissipation. Howeve...

We report a 72.8 GHz fully static frequency divider in AIInAs/InGaAs HBT IC technology. The CML divider operates with a 350 mV logic swing at less than OdBm input power up to a maximum clock rate of 63 GHz and requires 8.6 dBm of input power at the maximum clock rate of 72.8GHz. Power dissipation per flip-flop is 55mW with a 3.1V power supply. To our knowledge this is the highest frequency of o...

Wireless sensor nodes span a wide range of applications. This paper focuses on the biomedical area, more specifically on healthcare monitoring applications. Power dissipation is the dominant design constraint in this domain. This paper shows the different steps to develop a digital signal processing architecture for a single channel electrocardiogram application, which is used as an application...

Power dissipation due to leakage current in the digital circuits is a biggest factor which is considered specially while designing nanoscale circuits. This paper is exploring the ideas of reducing leakage current in static CMOS circuits by stacking the transistors in increasing numbers. Clearly it means that the stacking of OFF transistors in large numbers result a significant reduction in powe...

Optimization of testing power is a major significant task to be carried out in digital circuit design. Low power VLSI circuits dissipate more power during testing when compared with that of normal operation. As the feature size is scaled down with process technology advancement, power minimization has become a serious problem for the designers as well as the test engineers. Test vector reorderi...