A new asymmetric 6T-SRAM cell design is presented for low-voltage low-power operation under process variations. The write margin of the proposed cell is improved by the use of a new write-assist technique. Simulation results in 65 nm technology show that the proposed cell achieves the same RSNM as the asymmetric 5T-SRAM cell and 77% higher RSNM than the standard 6T-SRAM cell while it is able to...

Bias Temperature Instability (BTI) causes significant threshold voltage shift in MOSFET using Hafnium-dioxide (HfO2) High-k dielectric material. Negative BTI and Positive BTI are two types of BTI effects observed in p-channel and n-channel MOSFET. BTI affects the stability and reliability of conventional six transistor (6T) SRAM design in nano-scale CMOS technology. Eight transistor (8T) and Te...

This paper presents a proposed NMOS-centered 6T SRAM cell layout that reduces a neutron-induced multiple-cell-upset (MCU) SER on a same wordline. We implemented an 1-Mb SRAM macro in a 65-nm CMOS process and irradiated neutrons as a neutron-accelerated test to evaluate the MCU SER. The proposed 6T SRAM macro improves the horizontal MCU SER by 67–98% compared with a general macro that has PMOS-c...

Secret keys are usually stored in an nonvolatile memory, which can be hard to secure. An alternative is to generate the keys “on-the-fly” by using the inherent uniqueness of a device based on the manufacturing process variations. This is realized by physical unclonable functions (PUFs). A promising approach is to construct an intrinsic PUF based on SRAM memory, since many electronic devices hav...

Sub-threshold leakage and process-induced variations in bulk-Si technology limit the scaling of SRAM into sub-32 nm nodes. New device architectures are being considered to improve control Vt and reduce short channel effects. Among the likely candidates, FinFETs are the most attractive option because of their good scalability and possibilities for further SRAM performance and yield enhancement t...

Due to continuous scaling of CMOS, stability is a prime concerned for CMOS SRAM memory cells. As scaling will increase the packing density but at the same time it is affecting the stability which leads to write failures and read disturbs of the conventional 6T SRAM cell. To increase the stability of the cell various SRAM cell topologies has been introduced, 8T SRAM is one of them but it has its...

As the technology is improving , channel length of MOSFET is scaling down. In this environment stability of SRAM becomes the major concern for future technology. Static noise margin (SNM)[1] plays a vital role in stability of SRAM[2]. This paper gives an introduction to the “8T SRAM cell”[3]. It includes the Implementation, characterization and analysis of 8T SRAM cell and its comparison with t...

As modern technology is spreading fast, it is very important to design low power, high performance, fast responding SRAM(Static Random Access Memory) since they are critical component in high performance processors. In this paper we discuss about the noise effect of different SRAM circuits during read operation which hinders the stability of the SRAM cell. This paper also represents a modified ...

This paper addresses a, novel eight transistor (8T) CMOS SRAM cell design to enhance the stability and to reduce dynamic and leakage power. For the validation of proposed 8T SRAM cell, compared results with reported data. The parameters used in the proposed cell are comparable to the existing 8T SRAM cell at same technology and design rules. The stability of the proposed cell has been analyzed ...

Memories are a core part of most of the electronic systems. Performance in terms of speed and power dissipation is the major areas of concern in today’s memory technology. In this paper SRAM cells based on 6T, 7T, 8T, and 9T configurations are compared on the basis of performance for read and write operations. Studied results show that the power dissipation in 7T SRAM cell is least among other ...