نتایج جستجو برای: shielded planar circuits

تعداد نتایج: 128397  

Journal: :IEEE Transactions on Microwave Theory and Techniques 2020

Journal: :Progress In Electromagnetics Research C 2012

Journal: :Journal of Combinatorial Theory, Series B 1976

1999
Ahmed I. Khalil Alexander B. Yakovlev Michael B. Steer

An electric-field integral-equation formulation discretized via the method of moments (MoM) is proposed for the analysis of arbitrarily shaped planar conductive layers in a shielded guided-wave structure. The method results in a generalized scattering matrix (GSM) for the planar structure and can be used with other GSM’s, derived using this or other techniques, to model cascaded structures in w...

Journal: :Electronic Colloquium on Computational Complexity (ECCC) 2006
Nutan Limaye Meena Mahajan Jayalal Sarma

We re-examine the complexity of evaluating monotone planar circuits MPCVP, with special attention to circuits with cylindrical embeddings. MPCVP is known to be in NC, and for the special case of upward stratified circuits, it is known to be in LogDCFL. We characterize cylindricality, which is stronger than planarity but strictly generalizes upward planarity, and make the characterization partia...

2000
Enrique Drake Rafael R. Boix Tapan K. Sarkar

In this paper, we carry out a full-wave analysis of shielded two-port microstrip circuits, in which the metallizations are embedded in a multilayered substrate that may contain isotropic dielectrics and/or anisotropic dielectrics. The Galerkin’s method in the spectral domain is applied for determining the current density on the metallizations of the circuits when their feeding lines are excited...

2005
ERIC GOLES A. Gajardo

We prove that in a two-dimensional Sandpile automaton, embedded in a regular infinite planar cellular space, it is impossible to cross information, if the bit of information is the presence (or absence) of an avalanche. This proves that it is impossible to embed arbitrary logical circuits in a Sandpile through quiescent configurations. Our result applies also for the non-planar neighborhood of ...

2006

This paper presents a systematic design for yield enhancement of asynchronous logic circuits using 3-D (3Dimensional) integration technology. In this design, the target asynchronous circuits on one planar device layer which is fabricated with aggressive technology, are built on fault tolerant graph models with extra spare resources, and can be reconfigured by autonomous reconfiguration logic on...

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