A domain extension algorithm to correct the comparator offsets of pipeline analog-to-digital converters (ADCs) is presented, in which the 1.5-bit/stage ADC quantify domain is extended from a three-domain to a five-domain. This algorithm is designed for high speed and low comparator accuracy application. The comparator offset correction ability is improved. This new approach also promises signif...

Owing to the limited calculation precision during digital signal processing, the intermediate stages’ signal-bit-width truncation should be executed to realize the conversion from high precision to low one. As method of direct truncation will degenerate the Spurious FreeDynamicRange (SFDR) performance of the output signal, this paper proposed that additional digital dither should be added befor...

This paper describes a baseband analog (BBA) chain for wireless local area network (WLAN) applications. For the given specifications of the receiver BBA chain, the optimum allocation of the gain and filter rejection of each block in a BBA chain is achieved to maximize the SFDR. The fully integrated BBA chain is fabricated in 0.13 μm CMOS technology. An input-referred third-order intercept point...

We demonstrate a Linearized Ring Assisted Mach-Zehnder Interferometer (L-RAMZI) modulator in a miniature silicon device. We measure a record high degree of linearization for a silicon device, with a Spurious Free Dynamic Range (SFDR) of 106dB/Hz²/³ at 1GHz, and 99dB/Hz²/³ at 10GHz.

Introduction The ADS5500 is a high-speed, pipeline, CMOS ADC with 14-bit resolution and a 125-MSPS sampling rate. In March 2004 Texas Instruments (TI) introduced the device, which is the first ADC in the world market with such high sampling speed and high resolution. The ADS5500 is suitable for applications such as wireless communication, test and measurement instrumentation, control systems, m...

A 1Gsample/s 6-bit flash A/D converter with a combined chopping and averaging technique for reduced distortion in 0.18μm CMOS (May 2005) Nikolaos Stefanou Chair of Advisory Committee: Sameer Sonkusale Hard disk drive applications require a high Spurious Free Dynamic Range (SFDR), 6-bit Analog-to-Digital Converter (ADC) at conversion rates of 1GHz and beyond. This work proposes a robust, fault-t...

A 14-bit 200MS/s current-steering DAC with a novel digital calibration technique called dynamic-mismatch mapping (DMM) is presented. Compared to traditional static-mismatch mapping and dynamic element matching, DMM reduces the nonlinearities caused by both amplitude and timing errors, without noise penalty. This 0.14μm CMOS DAC achieves a state-of-the-art performance of SFDR>78dBc, IM3<-83dBc a...

This paper describes a feedthrough reduction technique for a track-and-hold (T/H) circuit with a body-bias control circuit. We propose a T/H circuit with a feedthrough canceller. This circuit cancels a leaking signal to the output node through the parasitic capacitance by using an opposite-phase signal. The simulation results using 90-nm CMOS technology demonstrate a feedthrough of −89.4 dB and...

This work describes a 12b 120MS/s dual-channel SHAfree Nyquist ADC based on a mid-code calibration technique eliminating offset mismatch between channels. The prototype ADC achieves a peak SNDR of 61.1dB and a peak SFDR of 74.7dB for input frequencies up to 60MHz at 120MS/s. Also, the measured DNL and INL are within 0.30LSB and 0.95LSB, respectively. The ADC fabricated in a 0.13 m CMOS process ...

This paper presents a fully differential 1.2V 8-order inverter-based gm-C complex filter with 2.4MHz bandwidth and centered at 2.5MHz, designed in a 90nm CMOS process technology. Tuning is carried out through voltage controlled capacitors instead of transconductors, resulting in a significant improvement in terms of linearity. The filter presents attractive attributes in terms of power, IRR, SF...