Generally, to improve the multiplier’s performance radix-4 Booth algorithm is used decrease number of partial products (NOP) by half. Moreover, increased encoders as well decoders will subject more power usage. In this, a new kind pre-encoder design with reduced transistors proposed which could usage multiplier some extent and implement 16-bit for pre-encoders decoders. This helps reduce disabl...

This paper presents a high speed binary floating point multiplier based on Hybrid Method. To improve speed multiplication of mantissa is done using Hybrid method replacing existing multipliers like Carry Save Multiplier, Dadda Multiplier and Modified Booth Multiplier. Hybrid method is a combination of Dadda Multiplier and Modified Radix-8 Booth Multiplier. The design achieves high speed with ma...

Bit-serial multiply-accumulate units (MACs) play a crucial role in various hardware accelerator applications, including deep learning, image processing, and signal processing. Despite the advantages of bit-serial MACs, such as small footprint, full utilization, high frequency, their serial nature can lead to latency potentially compromised performance. This study investigates potential solution...

In this paper, we propose a new multiplier-and-accumulator (MAC) architecture for low power and high speed arithmetic. High speed and low power MAC units are required for applications of digital signal processing like Fast Fourier Transform, Finite Impulse Response filters, convolution etc. For improving the speed and reducing the dynamic power, there is a need to reduce the glitches (1 to 0 tr...

An exceptional moduli set Residue Number System (RNS) of high element go (DR) can accelerate the execution of very large word-length tedious increases found in applications like open key cryptography. The modulo 2-1 multiplier is normally the noncritical data path among all modulo multipliers in such high-DR RNS multiplier. This planning slack can be abused to diminish the framework region and ...

A special moduli set Residue Number System (RNS) of high Dynamic Range (DR) can speed up the execution of verylarge word-length repetitive multiplications found in applications like public key cryptography. The modulo 2n-1 multiplier is usually the noncritical datapath among all modulo multipliers in such high-DR RNS multiplier. This timing slack can be exploited to reduce the system area and p...

Viterbi decoders employed in digital wireless communications are complex and dissipate large amount of power. In this paper, we investigate power dissipation of Radix-4 Viterbi decoder and SST (Scarce State Transition) Radix-4 Viterbi decoder with changing the constraint length K (namely, K=3, 4). We presents a low power, high-rate Viterbi decoder using SST scheme and Radix-4 trellis. The SST m...

In this paper a novel architecture of multiplier and accumulator (MAC) for high speed arithmetic is presented. The architecture adopts radix-4 modified booth algorithm (MBA) and hybrid carry save adder, in which the accumulator that has the largest delay in MAC was merged into Carry save adder (CSA) block. The performance of final adder block, which determines critical path of the architecture,...