In this paper, we describe a novel circuit consisting of N + 1 MOS transistors and a single floating gate which computes n soft maximumof N current inputs and reflects the result in the output transistor. An intuitive description of the operation of the circuit is given. Data from a working two-input version of the circuit is presented and discussed. The circuit features a high output voltage s...

We describe a floating-gate trimmed 14-bit 300-MS/s current-steered digital-to-analog converter (DAC) fabricated in 0.25and 0.18m CMOS logic processes. We trim the static integral nonlinearity to 0.3 least significant bits using analog charge stored on floating-gate pFETs. The DAC occupies 0.44 mm of die area, consumes 53 mW at 250 MHz, allows on-chip electrical trimming, and achieves better th...

We consider the class of constant depth AND/OR circuits augmented with a layer of modular counting gates at the bottom layer, i.e AC◦MODm circuits. We show that the following holds for several types of gates G: by adding a gate of type G at the output, it is possible to obtain an equivalent probabilistic depth 2 circuit of quasipolynomial size consisting of a gate of type G at the output and a ...

We present a floating-gate based system for computing vector quantization (VQ), which is typically used for data compression and classification of signals to symbols. We present an architecture and resulting circuits which will enable direct programming / storage of weight vectors, as well as methods for adaptive VQ. We use an analog bump circuit to perform a continuous distance computation alo...

In this paper the experimental equipment for UV-programming of floating-gate circuits are presented along with initial results on concurrent UV-programming of digital floating-gate circuits. It is demonstrated that concurrent UV-programming is possible when using real-time reconfigurable gates (Universal Gates). It is also shown that openings in the passivation, enabling UV-programming, works t...

We have demonstrated on-chip learning in an array of floating-gate MOS synapse transistors. The array comprises one synapse transistor at each node, and normalization circuitry at the row boundaries. The array computes the inner product of a column input vector and a stored weight matrix. The weights are stored as floating-gate charge; they are nonvolatile, but can increase when we apply a row-...

Nano-floating gate memory devices were fabricated on a flexible plastic substrate by a low-temperature fabrication process. The memory characteristics of ZnO-based thin-film transistors with Al nanoparticles embedded in the gate oxides were investigated in this study. Their electron mobility was found to be 0.18 cm(2)/V·s and their on/off ratio was in the range of 10(4)-10(5). The threshold vol...

A floating gate charge-sharing circuit that can be electrically programmed for precise positive and negative voltage changes, and can be implemented in a standard CMOS VLSI process is presented. With the advantage of its longterm charge-retention, the floating gate charge-sharing circuit is suitable for providing a compact, non-volatile and high-precision analog trimming method to trim the offs...