A formal methodology for automatic hardwaresoftware partitioning and co-scheduling the tasks of an application between Microprocessor and Programmable Logic Devices (PLDs) has become emerging research area of hardware software co-design. The main objective of this research is to get full advantage of hardware utilization and speedup the application execution. Hardware software partitioning and ...

Since modern FPLD devices have very complex structure there is necessity to develop new methods that would allow fully exploiting the possibilities these devices offer. The paper presents a general method for the synthesis targeted to ROM-based implementation of sequential circuits using embedded memory blocks of programmable devices. The method is based on the serial decomposition concept and ...

reversible logic circuits have found emerging attentions in nanotechnology,optical computing, quantum computing and low power design. a programmablelogic array (pla) is a universal circuit which is used to implement combinationallogic circuits. the main part of a pla is its and array. in this study we propose twotypes of optimized reversible programmable logic array (rpla) circuits. the firstty...

Microelectronic system designers are increasingly capturing their designs using hardware description languages such as VHDL and Verilog. The designs are then most often synthesized into programmable logic devices such as eld-programmable gate arrays (FPGAs). This approach places the emphasis on high-level design which reduces time to market by relying on synthesis software and programmable logi...

Programmable logic devices (PLDs) are a critical component in embedded industrial designs. PLDs have evolved in industrial designs from providing simple glue logic, to using FPGAs as a coprocessor. This technique allows for I/O expansion and off-loads the primary microcontroller (MCU) or digital signal processor (DSP) device in applications such as communications, motor control, I/O modules, an...

Field-Programmable Gate Arrays (FPGAs) have become one of the key digital circuit implementation media over the last decade. A crucial part of their creation lies in their architecture, which governs the nature of their programmable logic functionality and their programmable interconnect. FPGA architecture has a dramatic effect on the quality of the final device’s speed performance, area effici...

We present a method for obtaining a minimal set of test configurations and their associated set of test patterns that completely tests re-programmable Programmable Logic Arrays (PLAs) including EEPROM, UV -EPROM, and SRAM based re-programmable PLAs typically found in Complex Programmable Logic Devices (CPLDs). The resultant set of test configurations and vectors detect all single and multiple s...