In this paper a dual voltage CMOS low power output pad is presented. The pads are the interface circuits between the core and the package pins of any integrated circuit. The power consumption of these pads it is a very important parameter for the global power consumption of the integrated circuit that includes them. The proposed pad includes a pre-driver and a final output stage including ESD(e...

In this paper, we present new results in the development of a broad-band spatial power-combining system implemented in a standard X-band waveguide environment. Using 24 off-the-shelf GaAs monolithic-microwave integrated-circuit (MMIC) power amplifiers integrated with tapered-slot antenna arrays, the new combining circuit produced up to 126-W maximum power output with a gain variation of 1.9 dB ...

There is enormous potential in combining the capabilities of the biological and the solid state to create hybrid engineered systems. While there have been recent efforts to harness power from naturally occurring potentials in living systems in plants and animals to power complementary metal-oxide-semiconductor integrated circuits, here we report the first successful effort to isolate the energe...

A CMOS four-quadrant analog multiplier circuit for neural networks integrated circuit implementation is presented. By applying differential balanced current mode signals (both for the input, output and weight signals) the multiplication function is easily implemented through two translinear loops. The multiplier exhibits low power consumption (the dc current is 250 nA under a differential power...

In this paper we present a new transistor sizing methodology called Free Power Recovery (FPR) for low power circuit design. The objective of this methodology is to minimize the total power of a circuit by accounting for node switching activities and leakage duty cycles (LDC). The methodology has been incorporated into the EinsTuner circuit tuning tool. EinsTuner automates the tuning process usi...

This paper proposes a gate driver integrated circuit to prevent breakdown of switching power amplifiers. The proposed circuit consists of a dead-time generator, level shifters, and a breakdown blocker. The dead-time generator makes non-overlapped input signals and the breakdown blocker detects instantaneous turned-on input signals and resets them to the off-state before the switching power cell...

In this paper, a low voltage CMOS current controlled floating resistor which is convenient for integrated circuit implementation is designed by using differential pair. The proposed resistor has a simple circuit structure and low power dissipation. This circuit is required ±0.75 V as a power supply. The basic advantages of this circuit are wide tuning range of the resistance value, satisfied fr...

In this paper are described simulation and measurement processes of a power switch cell used for single event latchup protection of a digital fault tolerant application specific integrated circuit. The standard IHP 250 nm simulation models of components are used for the performed analog simulation using the Virtuoso Cadence tools.

To meet the demanding requirements in the growing area of wireless sensing applications, some sensing platforms have included low-power application-specific hardware to process the sensor data for compression and pre-classification of the relevant information. While this additional hardware can reduce the overall power consumption of the system, a unique hardware solution is required for each a...