Based on the shifted polynomial basis (SPB), a high efficient bit-parallel multiplier for the field GF(2m) defined by an equallyspaced trinomial (EST) is proposed. The use of SPB significantly reduces time delay of the proposed multiplier and at the same time Karatsuba method is combined with SPB to decrease space complexity. As a result, with the same time complexity, approximately 3/4 gates o...

In the recent year growth of the portable electronics is forcing the designers to optimize the existing design for better performance. Multiplication is the most commonly used arithmetic operation in various applications like, DSP processor, math processor and in various scientific applications. In this paper a low power bypassing -based multiplier design is present, in which reduction in power...

In this paper, a double precision IEEE 754 floating-point multiplier with high speed and low power is presented. The bottleneck of any double precision floatingpoint multiplier design is the 53x53 multiplication of the mantissas (52 bit mantissa+1 hidden bit). This paper proposes a approach to improve this performance bottleneck by adding a redundant 54 bit initialized to ‘0’ in the mantissas o...

MTCMOS is an effective circuit level technique which has multiple threshold voltages in order to optimize delay and power. Low threshold voltage MOSFETs enhance the speed performance, while the high threshold voltages MOSFETs minimize the static leakage power. The above technique is adopted in parallel multiplier with level shifter interface which gives supply voltage for MTCMOS transistors. By...

Multiplication is frequently required in digital signal processing. Parallel multipliers provide a high-speed method for multiplication, but require large area for VLSI implementations. In most signal processing applications, a rounded product is desired to avoid growth in word size. Thus an important design goal is to reduce the area requirement of the rounded output multiplier. This paper pre...

This paper presents an extra regular, Two recently proposed designs, as the typical complexity-reduced, high-performance pipelined examples of the improved conventional architectures, multiplier architecture, using newly proposed multiplier are rectangular-styled wallace tree multiplier (RSWM triple-expansion schemes. It is based on a parallel for short)) [2] and limited switch dynamic logic co...

Reversible logic is one of the new paradigms for power optimization that can be used instead of the current circuits. Moreover, the fault-tolerance capability in the form of error detection or error correction is a vital aspect for current processing systems. In this paper, as the multiplication is an important operation in computing systems, some novel reversible multiplier designs are propose...

Using the self duality of an optimal normal basis (ONB) of type II, we present a bit parallel systolic multiplier over GF (2) which has a low hardware complexity and a low latency. We show that our multiplier has a latency m + 1 and the basic cell of our circuit design needs 5 latches (flip-flops). On the other hand, most of other multipliers of the same type have latency 3m and the basic cell ...

The objective of the paper is to reduce the hardware complexity of higher order FIR filter with symmetric coefficients. The aim is to design an efficient Fast Finite-Impulse Response (FIR) Algorithms (FFAs) for parallel FIR filter structure, with a constrain that the filter tap must be multiple of 2. In our work we have briefly discussed for L=4 parallel implementation. The parallel FIR filter ...

This paper presents Field Programmable Gate Array (FPGA) implementation of standard and truncated multipliers using Very High Speed Integrated Circuit Hardware Description Language (VHDL). Truncated multiplier is a good candidate for digital signal processing (DSP) applications such as finite impulse response (FIR) and discrete cosine transform (DCT) etc. Significant reduction in FPGA resources...