Due to advances in fiber-optics and VLSI technology, interconnection networks which allow multiple simultaneous broadcasts are becoming feasible. In such large systems hot-spot contention can occur when several processors concurrently request access to one data structure with resulting severe performance degradation. To minimize the effect of hot-spots in the broadcast architecture, messages ar...

W ith the rapid advances in technol'VV ogy, it is now feasible to build a system consisting of hundreds or thousands of processors. Processors in such a parallel/distributed system may spend a considerable amount of time just communicating among themselves unless an efficient interconnection network (IN) connects them. A complete interconnection such as crossbar may be cost prohibitive, but a s...

This paper describes the interconnection network used in the Cray T3E multiprocessor. The network is a bidirectional 3D torus with fully adaptive routing, optimized virtual channel assignments, integrated barrier synchronization support and considerable fault tolerance. The routers are built with LSI’s 500K ASIC technology with custom transmitters/ receivers driving low-voltage differential sig...

1. Abstract Due to advances in fiber-optics and VLSI technology, interconnection networks which allow multiple simultaneous broadcasts are becoming feasible. The performance of a multiprocessor system based on a broadcast interconnection network is examined using analytical models and simulation under the message-passing and distributed-shared-memory paradigms and is compared to similar perform...

Next to the high performance, the most important feature of the multiprocessor systems is their fault tolerant capability. In this regard, fault tolerant interconnection networks and specially fault tolerant routing methods are important parts of these systems. Hypercube is a popular interconnection network that is used in many multiprocessors. There are a number of suggested methods for fault ...

A deadlock-free routing algorithm can be generated for arbitrary interconnection networks using the concept of virtual channels. A necessary and sufficient condition for deadlock-free routing is the absence of cycles in a channel dependency graph. Given an arbitrary network and a routing function, the cycles of the channel dependency graph can be removed by splitting physical channels into grou...

We demonstrate the feasibility of the data vortex interconnection network architecture for use in supercomputing by emulating realistic network traffic on an eight-node subnetwork. The evaluation workload uses memory accesses from the Barnes–Hut application in the SLPASH-2 parallel computing benchmark suite, which was extracted by using the M5 multiprocessor system simulator. We confirm that tr...

Packaging constraints motivate a two-level interconnection network for a multiprocessor. A single node in the global network contains multiple processors connected by a local network. An important issue in two-level networks is how alternative numbers of processors per node changes the per link traac in the global network. In the case of a hypercube global network we consider three communicatio...

Recent developments of coarse WDM optoelectronic components will allow for the fabrication of low cost, high-speed reconfigurable interconnection networks within large distributed sharedmemory (DSM) multiprocessor machines, by using the wavelength tunability in combination with a broadcast-and-select mechanism. We discuss in this work the advantages and the limitations they impose on network pe...