Communication systems use the concept of transmitting information using the electrical distribution network as a communication channel. To enable the transmission data signal modulated on a carrier signal is superimposed on the electrical wires. Typical power lines are designed to handle 50/60 Hz of AC power signal; however they can carry the signals up to 500 KHz frequency. This work aims to a...

in this work, the time series modeling was used to predict the tazareh coal mine risks. for this purpose, initially, a monthly analysis of the risk constituents including frequency index and incidence severity index was performed. next, a monthly time series diagram related to each one of these indices was for a nine year period of time from 2005 to 2013. after extrusion of the trend, seasonali...

With the development of power switches and processor performance in recent years, control frequency inverters has been significantly improved. However, limited by technology price, sensor sampling large-scale industrial applications is much lower than inverter that can be realized. This mismatch limits improvement inverter. In this article, current voltage at non-sampling time are reconstructed...

A pipelined ADC incorporates a precharged resistor-ladder DAC in a multi-bit front-end, achieving fast settling and allowing calibrationof both dynamic and static gain errors. Using simple differential pairs with a gain of 5 as op amps and realized in 65-nm CMOS technology, the 10-bit ADC consumes 36 mW at a sampling rate of 1 GHz and exhibits an SNDR of 52.7 dB at an input frequency of 490 MHz.

In this paper. we propose a baseband OFDM receiver for highspeed wireless local area network defined in IEEE 802.1 la physical layer. Algorithms for channel estimation/equalization. timing recovery, carrier frequency acquisition/tracking, and sampling clock tracking are individually designed and later integrated into a receiver architecture. Simulation results show that the proposed OFDM receiv...

JOSEPH, BALU High-Speed Transceiver Design in CMOS using Multilevel (4-PAM) Signaling. (Under the direction of Dr. Wentai Liu) The design of a 4 Gbps serial link transceiver in 0.35μm CMOS process is presented. The major factors limiting the performance of high-speed links are transmission channel bandwidth, timing uncertainty and on-chip frequency limitations. The design uses a combination of ...