Performance monitor (PM) support in on-chip PowerPC@’ microprocessors is used to analyze processor, software, and system attributes for a variety of workloads. The interface to the PowerPC 604@ microprocessor, which we abbreviate “604,” has been externalized to end users. We discuss the enhanced PM support available in an upgrade of the 604, the PowerPC m e T M microprocessor, which we abbrevia...

This paper presents a System-on-a-Chip design methodology that uses a microprocessor subsystem as a building block for the development of chips for networking applications. The microprocessor subsystem is a self-contained macro that functions as an accelerator for computation-intensive pieces of the application code, and complements the standard components of the SoC. It consists of processor c...

CMP, chip multiprocessor, embedded processor, embedded DRAM, CPACM MPOC was an ambitious microprocessor project undertaken at Hewlett Packard's Palo Alto Research Lab from about 1998 until early in the year 2001. MPOC was designed to be a single-chip community of identical high-speed RISC processors surrounding a large common storage area. Each processor would have its own clock, cache and prog...

RECENT TREND in commercial platforms is the integration of on-chip, configurable logic (also known as FPGAs) with a microprocessor. Examples include 8-bit platforms, such as Triscend's E5 and Atmel's FPSLIC (Field-Programmable System-Level IC); and 32-bit platforms , such as Triscend's A7, Xilinx's Virtex II Pro, and Altera's Excalibur. A main benefit of on-chip configurable logic is that it su...

Today’s leading edge microprocessors like the Intel’s Itanium 2 Processor feature over 220 million transistors in 0.18μm semiconductor process technology. Nanotechnology that continues to drive Moore’s Law provides a doubling of the transistor density every two years. This indicates that a Billion transistor chip is possible in the 65 nm technology within the next 3 to 4 years. Such chips can b...

Chip Multi-Processor (CMP) has recently become a mainstream microprocessor. CMP’s allow multiple threads executing on a single processor chip at the same time, thus promise to deliver higher throughput performance. However, resource sharing among the threads executing on the same processor chip can cause conflicts and hurt the performance. Thus obtaining high performance and scalability on CMP ...

In this paper we explore the potential of reducing the cache size of the cores in the DDM-CMP architecture and implementing additional on-chip processors in the space saved. With this technique we almost double the already high speedup the DDM-CMP architecture has compared to a state-of-the-art high-end single chip microprocessor. The proposed DDM-CMP scheme achieves speedup ranging from 5.2 to...

Because of their widespread use, general purpose microprocessors are called upon to execute an increasingly diverse set of applications. Due to their static organization , these devices often operate very ineeciently under these conditions, which results in lost performance opportunities and extra energy dissipation. By exploiting the partitioning of major microprocessor hardware structures, an...

Microprocessor packaging in modern workstations and servers often consists of one or more large flip chip die that are mounted to a high performance ceramic chip carrier. The final assembly configuration features a complex stack up of area array solder interconnects, underfill, ceramic substrate, lid, heat sink, thermal interface materials, second level solder joints, organic PCB, etc., so that...

AMULET1 demonstrated the feasibility of building an asynchronous implementation of the ARM microprocessor. Although functional, this first asynchronous ARM microprocessor did not fully exploit the potential of the asynchronous design style to deliver improved performance and power consumption. This paper describes AMULET2e, an embedded system chip incorporating an enhanced asynchronous ARM core...