full adder cell is often placed in the critical path of other circuits. therefore it plays an important role in determining the entire performance of digital system. moreover, portable electronic systems rely on battery and low-power design is another concern. in conclusion it is a vital task to design high-performance and low-power full adder cells. since delay opposes against power consumptio...

SUMMARY This paper proposes a low power scan test scheme and formulates a problem based on this scheme. In this scheme the flip–flops are grouped into N scan chains. At any time, only one scan chain is active during scan test. Therefore, both average power and peak power are reduced compared with conventional full scan test methodology. This paper also proposes a tabu search–based approach to m...

The ever-increasing test data volume and test power consumption are the two major issues in testing of digital integrated circuits. This paper presents an efficient technique to reduce test data volume and test power simultaneously. The pre-generated test sets are divided into two groups based on the number of unspecified bits in each test set. Test compression procedure is applied only to the ...

In our project, we propose a novel architecture which generates the test patterns with reduced switching activities. LP-TPG (Test pattern Generator) structure consists of modified low power linear feedback shift register (LP-LFSR), m-bit counter; gray counter, NOR-gate structure and XOR-array. The m-bit counter is initialized with Zeros and which generates 2m test patterns in sequence. The m-bi...

A generic built-in self-test needed for SoC devices implementing for low power consumption. In this we proposed a new technique to generate a fully pre-computed test set in a deterministic BIST using simple gray counter within a reasonable clock cycles. Conversely, we consider only a small part of the circuit which is to be tested is active and the other parts of the circuit are fed with low le...

729 Abstract— Power consumption during testing System-On-Chip (SOC) is becoming increasingly important as the IP core increases in SOC. We present a new algorithm to reduce the scan-in power using the modified scan latch reordering and clock gating. We apply scan latch reordering technique for minimizing the hamming distance in scan vectors. Also, during scan latch reordering, the don't care in...

Low Power Design is a critical concern and metric for today's complex designs. During scan based manufacturing test, power dissipation becomes even more critical as the chip may not have been designed to tolerate excessive switching during scan test. Excessive power dissipation during scan test can result in excessive voltage variations, reduced noise margins and other signal integrity issues w...

conclusions accordingly, laser therapy in our protocol seemed to affect some of the nerve growth parameters, mostly on motor rather than sensory fibers. results in the two -point discrimination- test, there was no significant difference between the two groups in the thumbs but a significant improvement was observed in the index finger of the lt group. improvement of muscular examinations such a...