This paper proposes a low voltage (±0.55V supply voltage) low power (44.65µW) high common mode rejection ratio (CMRR) differential amplifier (d.a.) with rail to rail input common mode range (ICMR), constant transconductance (gm) and enhanced frequency performance. Its high performance is obtained using a simple negative averaging method so that it cancels out the common mode input signals at th...

This paper presents a two-stage low-noise ultra-wideband amplifier to obtain high and smooth gain in 180nm CMOS Technology. The proposed structure has two common source stages with inductive feedback. First stage is designed about 3GHz frequency and second stage is designed about 8GHz. In simulation, symmetric inductors of TSMC 0.18um CMOS technology in ADS software is used.Simulations results ...

This paper presents the design, fabrication and performance of a three-stage 155GHz monolithic low noise amplifier (LNA) using 0.1 -pm pseudomorphic (PM) InAIAs/InGaAs/InP HEMT technology. This amplifier exhibits a measured small signal gain of 12 dB at 155 GHz, and more than 10 dB gain from 151 to 156 GHz. When this amplifier is biased for low noise figure, a noise figure of 5.1 dB with associ...

Most low noise amplifier designs focus on eliminating sources of noise that are intrinsic to the amplifier (thennal noise, Ilfnoise). As integrated drcuit design moves increasingly towards mixed signal implementations, the design of low-noise analog amplifiers must be re...evaluated to consider the switching noise generated by on-<:hip digital circuitry. We designed three fully differential ver...