Asynchronous quasi-delay-insensitive (QDI) NoCs have several advantages over their clocked counterparts. Virtual channel (VC) is the most utilized flow control method in asynchronous routers but spatial division multiplexing (SDM) achieves better throughput performance for best effort traffic than VC. A novel asynchronous SDM router architecture is presented. Area and latency models are provide...

Tor is the most popular low-latency anonymity network for enhancing ordinary users’ online privacy and resisting censorship. While it has grown in popularity, Tor has a variety of performance problems that result in poor quality of service, a strong disincentive to use the system, and weaker anonymity properties for all users. We observe that one reason why Tor is slow is due to lowbandwidth vo...

The era of single processors had almost reached a saturation state, and the industry moved to multi-core for newer generation many-core architecture. Interconnections between multiple cores with network on chip (NoC) surpass traditional bus architecture its quality service (QoS) other additional services. Seamless communication among is more significant better performance proper utilization cor...

Emerging parallel real-time and multimedia applications broaden the range of performance requirements imposed on the inter-connection network. This communication typically consists of a mixture of diierent traac classes, where guaranteed packets require bounds on latency or throughput while good average performance suuces for the best-eeort traac. This paper investigates how multicomputer route...

In this paper, we propose a design methodology for faulttolerant adaptive routers for parallel and distributed computers. The key idea of our method is integrating minimal and non-minimal routing that is supported by independent virtual channels (VCs). Distinguishing the routing functions for each set of VCs simplifies the design of fault-tolerant algorithms. After describing the method, we sho...

Future high-speed switches and routers will be expected to support a large number of ports at high line rates carrying traffic with diverse statistical properties. Accordingly, scheduling mechanisms will be required to handle Tbit/sec aggregated capacity while providing quality of service (QoS) guarantees. In this paper a novel high-capacity switching scheme for ATM/WDM networks is presented. T...

There is a growing need for routers to support multicast and broadcast applications such as war gaming, teleconferencing and web casting. Using the natural parallelism of optics in a switching core, high-performance routers that are efficient for heavily multicast/broadcast traffic can be implemented. A broadcast and select based optical switching core can handle efficiently multicast/broadcast...

An FPGA based, Reconfigurable 3x3 router for both 1-D and 2-D network on chip architectures design is proposed. The design is highly scalable and exploits the features provided by any standard FPGA platform and can be easily ported to an ASIC or any other FPGA platform. These routers are reconfigurable and they are capable of transmitting both 1D and 2D packets throughout the network, this redu...

Many organizations have the mission of assessing the quality of broadband access services offered by Internet Service Providers (ISPs). They deploy network probes that periodically perform network measures towards selected Internet services. By analyzing the data collected by the probes it is often possible to gain a reasonable estimate of the bandwidth made available by the ISP. However, it is...

Detecting and localizing latency-related problems at router and switch levels is an important task to network operators as latency-critical applications in a data center network become popular. This however requires that measurement instances must be deployed at each and every router/switch in the network. In this paper, we study a partial deployment method called Reference Latency Interpolatio...