The high leakage current in deep submicron regimes is becoming a significant contributor to the power dissipation of CMOS circuits as the threshold voltage, channel length, and gate oxide thickness are reduced. Consequently, the identification and modeling of different leakage components is very important for the estimation and reduction of leakage power, especially in the low power application...

Gate leakage currents in AlGaN/GaN heterostructure field-effect transistor ~HFET! structures with conventional and polarization-enhanced barriers have been studied. Comparisons of extensive gate leakage current measurements with two-dimensional simulations show that vertical tunneling is the dominant mechanism for gate leakage current in the standard-barrier HFET and that the enhanced-barrier s...

We report an effective method for bringing about a significant reduction in the lateral leakage current passing through the non-channel region of an organic semiconductor through an organic solvent vapor treatment. The hydroxyl-containing dimethyl-sulfoxide molecules interrupt the bulk charge transport after undergoing solvent vapor treatment and reduce the lateral leakage current effectively, ...

Gate dielectric leakage current becomes a serious concern as sub-20Å gate oxide prevails in advanced CMOS processes. Oxide this thin can conduct significant leakage current by various direct-tunneling mechanisms and degrade circuit performance. While the gate leakage current of MOS capacitors has been much studied, little has been reported on compact MOSFET modeling with gate leakage. In this w...

The main idea of this paper is to discuss a new approach to optimize the value of leakage current in MOS transistors. It based on looking for optimal values of the main SPICE parameters which influence the value of the leakage current. These Values make in totally the leakage current, minimal value. The logic and the flow diagrams seem working correctly; various simulation results show the vali...

| Low supply voltage requires the device threshold to be reduced in order to maintain performance. Due to the exponential relationship between leakage current and threshold voltage in the weak inversion region, leakage power can be no longer negligible in such circuits. In this paper we present a technique to accurately estimate leakage power by accurately modeling the leakage current in transi...

A SRAM cell must meet requirements for operation in submicron. As the density of SRAM increases, the leakage power has become a significant component in chip design. The power Consumption is a major issue of today's CMOS Technology. Leakage power is major issue for short channel devices. As the technology is shrinking the leakage current is increasing very fast. so, several methods and techniqu...