The present paper addresses whether topographical jitter or undersampling might limit pattern perception in foveal, peripheral and strabismic amblyopic vision. In the first experiment, we measured contrast thresholds for detecting and identifying the orientation (up, down, left, right) of E-like patterns comprised of Gabor samples. We found that detection and identification thresholds were both...

Copyright (c) 2007 IEEE. Personal use of this material is permitted. However, permission to use this material for any other purposes must be obtained from the IEEE by sending an email to [email protected]. 1 Abstract— In this paper, a fully integrated OC-192 clock-data recovery (CDR) architecture in standard 0.18 m CMOS is described. The proposed architecture integrates the typically la...

As the communication speed/data rate approaches 1 Gb/s and beyond, timing jitter and amplitude noise become the major limiting factors for system performance. Traditional methods used in simulating, analyzing, modeling, and quantifying jitter and noise in terms of peak-to-peak and/or RMS become no longer accurate and sufficient. As such, new methods with better accuracy and comprehension are ca...

Clock (CLK) generators and synthesizers form the pulse of a complex digital system and errors in a clock's signal quality can have wide-ranging effect. One of the most important performance measurements is clock jitter. Jitter is defined as "the short-term variation of a signal with respect to its ideal position in time." In a clock generator chip, there are many factors which contribute to out...

For the problem that general characteristic impedance measurement instrument is difficult to measure the size of clock jitter, this paper proposes a measurement algorithm to achieve clock jitter based on sequential equivalent sampling. First, according to the relationship between the equivalent sampling signal and the average signal, we count up the probability density distribution of the clock...

A 10Gb/s Full On-chip Bang-Bang Clock and Data Recovery System Using an Adaptive Loop Bandwidth Strategy. (August 2009) Hyung-Joon Jeon, B.S., Seoul National University Chair of Advisory Committee: Dr. Jose Silva-Martinez As demand for higher bandwidth I/O grows, the front end design of serial link becomes significant to overcome stringent timing requirements on noisy and bandwidthlimited chann...

The line jitter of CCD images can considerably influence the precision and resolution of a high-accuracy vision-based automated inspection system. We report the experimental studies on the line jitter of CCD images. By use of a method of Harr wavelet transform, correlation, and statistics analysis to detect the line jitter of subpixels, the experiment reveals that the line jitter exhibits inher...

A synchronization scheme for extraction of low-jitter rf signals from optical pulse trains, which is robust against photodetector nonlinearities, is described. The scheme is based on a transfer of timing information into an intensity imbalance of the two output beams from a Sagnac loop. Sub-100-fs timing jitter between the extracted 2-GHz rf signal and the 100-MHz optical pulse train from a mod...

For the problem that general characteristic impedance measurement instrument is difficult to measure the size of clock jitter, this paper proposes a measurement algorithm to achieve clock jitter based on sequential equivalent sampling. First, according to the relationship between the equivalent sampling signal and the average signal, we count up the probability density distribution of the clock...

In this paper a new architecture for delay locked loops will be presented.  One of problems in phase-frequency detectors (PFD) is static phase offset or reset path delay. The proposed structure decreases the jitter resulted from PFD by switching two PFDs. In this new architecture, a conventional PFD is used before locking of DLL to decrease the amount of phase difference between input and outpu...