The recent emerging of commercial high-level synthesis tools raises the question of specifying IPs at the algorithmic, or behavioral, level. High-level synthesis allows fast exploration of various architectural solutions from a single behavioral description. While flexibility of currently used soft IPs is limited to optimizing the logic synthesis flow, behavioral IPs introduce architectural fle...

Classical strategies in design for testability are applied at the gate-level, after the RT-logic synthesis process. New techniques covering test and synthesis (Test Synthesis) [1] are appearing but their application is mainly oriented to gate level (commercial tools such as Synopsys). On the other hand, most high-level synthesis tools do not take into account the testability of the final archit...

The task of a high-level behavioural synthesis system is to create a structure to implement a given abstract specification of behaviour. The behaviour is specified at the algorithmic level, typically in the form of a high-level programming language. The synthesized structure is described at the register-transfer level. In such systems the synthesis task is guided only by the behaviour and some ...

Producing efficient circuits from high-level language descriptions remains a problem. This paper proposes three techniques for improving the quality of circuits generated from high-level Esterel specifications, a synchronous, concurrent language designed to specify control-dominated systems. Together, the three techniques aim to improve the quality of the input to logic synthesis to produce bet...

This paper presents techniques to integrate the use of variable-latency units in a high-level synthesis (HLS) design methodology. Components used as building blocks (e.g., functional units) in conventional HLS techniques are assumed to have fixed latency values. Variable-latency units exhibit the property that the number of cycles taken to compute their outputs varies depending on the input val...

In this essay we discuss the origin, central results, and some perspectives of algorithmic synthesis of nonterminating reactive programs. We recall the fundamental questions raised more than 50 years ago in “Church’s Synthesis Problem” that led to the foundation of the algorithmic theory of infinite games. We outline the methodology developed in more recent years for solving such games and addr...

High Level Synthesis for Packet Processing Pipelines

ABSTRACT This paper presents an efficient method to design cascaded Σ∆ modulators implemented with continuous-time circuits. Instead of using a discrete-to-continuous time transformation, the proposed methodology is based on the direct synthesis of the whole cascaded architecture. This leads to more efficient topologies in terms of circuit complexity, power consumption and robustness with respe...

This paper presents the detailed survey of the Memory, Power and Temperature optimization techniques in the High Level Synthesis presented in the research literature.

This paper introduces a new methodology to evaluate datapath interconnection schemes at the behavioral level. This evaluation model is validated by comparison with RTL synthesis evaluation results. It has been implemented and used for architecture exploration in order to select the best interconnection scheme to use. A generic datapath model capable of representing a variety of interconnection ...