In this paper a new technique is proposed based on the comparison between Conventional Transistorized Flip-flop and Data transition Look ahead D flip flop here we are checking the working of DLDFF and the conventional D Flip-flop after that we are analyzing the characteristic comparison using power & area constraints after that we are proposing a Negative Edge triggered flip-flop named as Switc...

In this paper we present an ILP-based method to simultaneously assign supply and threshold voltages to individual gates for dynamic and leakage power minimization. In our three-step approach, low power min-flipflop (FF) retiming is first performed to reduce the clock period while taking the FF delay/power into consideration. Next, the subsequent voltage assignment formulated in ILP makes the be...

New designs for Hybrid latch flip-flip (HLFF) and implicit-pulsed data-close-to-output (ip-DCO) flipflop circuits are proposed to improve the redundant switching activity, speed and power as these flip-flop circuits are basic building blocks of many timing elements. This paper evaluates and compares the performance of various flip-flop circuits which can reduce the effect of redundant switching...

Detection of crosstalk induced glitch faults is important as they can result in erroneous output if the glitch effect propagates to a primary output or to an intermediate flipflop. A new method is thus presented in this paper to generate test patterns for crosstalk induced glitch faults followed by compaction of the test set. By considering the spatial and temporal aspects between the victim an...

We present an optical shift register that consist out of two serially connected optical flip-flop memories driven by common clock pulses. Each optical flip-flop consists out of two ring lasers sharing a single active element, which makes the optical flip-flops easily cascade with each other. The two cascaded optical flip-flops are controlled by the clock pulses in such a way that the input data...

For the past several years, much progress has been made in Low power VLSI Design .In This paper ,a novel low-power pulse Triggered flipflop design is presented. First, the pulse generation control logic an AND function, is removed from critical path to facilitate a faster discharge operation. A simple two-transistor AND gate design is used to reduce the circuit complexity. Second, a conditional...

In this paper, a new metastability immune warning detection flipflop (FF) is proposed, which consists of an edge detector, a warning window creator, and a caution detector along with a resilient circuit. The delayed data are monitored during the warning window to flag a warning signal before the data enter the erroneous zone. In this scheme, the warning window is self-governing of input clock f...